Add a Dram accumulation example.

CMakeLists.txt

@@ -117,6 +117,7 @@ if (DEFINED ENV{MAXCOMPILERDIR} AND DEFINED ENV{MAXELEROSDIR})
   add_fpga_build(LinearAlgebra AdjustedCSRSpMV SpmvBase fpgaNaiveManager)
   add_fpga_build(LinearAlgebra CsrDecoder CsrDecoder CsrDecoderManager)
   add_fpga_build(LinearAlgebra ParallelCsrDecoder ParallelCsrDecoder ParallelCsrDecoderManager)
+  add_fpga_build(Tests DramAccumulator DramAccumulator DramAccumulatorManager)
 
   # --- Tests
   add_fpga_test(LinearAlgebra DenseMatrixVectorMultiply)
@@ -140,6 +141,7 @@ if (DEFINED ENV{MAXCOMPILERDIR} AND DEFINED ENV{MAXELEROSDIR})
 #  this project is designed not to compile:
 #  add_fpga_test(Tests ManagerPropertyPassThrough)
   add_fpga_test(Tests NestedClass)
+  add_fpga_test(Tests DramAccumulator)
   add_fpga_test(LanguageFeatures PackUnpack)
   add_fpga_test(LanguageFeatures NestedCounterVariableBoundary)
   add_fpga_test(Infrastructure BRAMReadWrite)

src/com/custom_computing_ic/dfe_snippets/manager/ManagerUtils.java

@@ -98,5 +98,12 @@ public static void addLinearStreamFromLmemToKernel(CustomManager m, KernelBlock
         name,
         MemoryControlGroup.MemoryAccessPattern.LINEAR_1D);
   }
+
+  public static void addLinearStreamFromKernelToLmem(CustomManager m, KernelBlock kernel, String name) {
+    m.addStreamToOnCardMemory(
+        name,
+        MemoryControlGroup.MemoryAccessPattern.LINEAR_1D) <== kernel.getOutput(name);
+  }
+
 }
 

test/Tests/DramAccumulator/src/DramAccumulatorCpuCode.cpp

@@ -0,0 +1,43 @@
+#include <stdio.h>
+
+#include <vector>
+#include <iostream>
+
+#include "DramAccumulator.h"
+#include "MaxSLiCInterface.h"
+
+int main(void)
+{
+
+  const int inSize = 384 * 70;
+
+  std::vector<int> a(inSize), expected(inSize), out(inSize, 0);
+
+  int iterations = 2;
+  int k = 5;
+  for(int i = 0; i < inSize; ++i) {
+    a[i] = i + 1;
+    expected[i] = a[i] + k * iterations;
+  }
+
+  std::cout << "Running on DFE." << std::endl;
+  DramAccumulator_write(
+      a.size() * sizeof(int),
+      0,
+      (uint8_t *)&a[0]);
+  DramAccumulator(a.size(), iterations, k);
+  DramAccumulator_read(
+      out.size() * sizeof(int),
+      0,
+      (uint8_t *)&out[0]);
+
+  for (int i = 0; i < inSize; i++)
+    if (out[i] != expected[i]) {
+      printf("Output from DFE did not match CPU: %d : Got %d != Exp %d\n",
+        i, out[i], expected[i]);
+      return 1;
+    }
+
+  std::cout << "Test passed!" << std::endl;
+  return 0;
+}

test/Tests/DramAccumulator/src/DramAccumulatorKernel.maxj

@@ -0,0 +1,17 @@
+import com.maxeler.maxcompiler.v2.kernelcompiler.Kernel;
+import com.maxeler.maxcompiler.v2.kernelcompiler.KernelParameters;
+import com.maxeler.maxcompiler.v2.kernelcompiler.types.base.DFEVar;
+
+class DramAccumulatorKernel extends Kernel {
+
+    protected DramAccumulatorKernel(KernelParameters parameters) {
+        super(parameters);
+
+        DFEVar a = io.input("a", dfeUInt(32));
+
+        DFEVar k = io.scalarInput("k", dfeUInt(32));
+
+        io.output("output", a + k, dfeUInt(32));
+    }
+
+}

test/Tests/DramAccumulator/src/DramAccumulatorManager.maxj

@@ -0,0 +1,77 @@
+import com.maxeler.maxcompiler.v2.managers.engine_interfaces.CPUTypes;
+import com.maxeler.maxcompiler.v2.managers.engine_interfaces.EngineInterface;
+import com.maxeler.maxcompiler.v2.managers.engine_interfaces.InterfaceParam;
+import com.maxeler.maxcompiler.v2.managers.custom.CustomManager;
+import com.maxeler.maxcompiler.v2.managers.custom.blocks.KernelBlock;
+import com.maxeler.maxcompiler.v2.build.EngineParameters;
+import com.maxeler.maxcompiler.v2.managers.custom.stdlib.MemoryControlGroup;
+
+import com.custom_computing_ic.dfe_snippets.manager.ManagerUtils;
+
+public class DramAccumulatorManager extends CustomManager{
+
+    private static final String s_kernelName  = "DramAccumulatorKernel";
+
+    DramAccumulatorManager(EngineParameters ep)
+    {
+        super(ep);
+
+        KernelBlock k = addKernel(new DramAccumulatorKernel(makeKernelParameters(s_kernelName)));
+
+        ManagerUtils.addLinearStreamFromLmemToKernel(this, k, "a");
+        ManagerUtils.addLinearStreamFromKernelToLmem(this, k, "output");
+
+        addStreamToCPU("tocpu") <== addStreamFromOnCardMemory("lmem2cpu",
+            MemoryControlGroup.MemoryAccessPattern.LINEAR_1D);
+        addStreamToOnCardMemory("cpu2lmem",
+            MemoryControlGroup.MemoryAccessPattern.LINEAR_1D) <==
+        addStreamFromCPU("fromcpu");
+    }
+
+    private static EngineInterface interfaceDefault() {
+        EngineInterface ei = new EngineInterface();
+        CPUTypes type = CPUTypes.INT32;
+        int size = type.sizeInBytes();
+
+        InterfaceParam N = ei.addParam("N", CPUTypes.INT);
+        InterfaceParam nIterations = ei.addParam("iterations", CPUTypes.INT);
+        InterfaceParam ZERO = ei.addConstant(0);
+
+        InterfaceParam sizeBytes = N * size;
+
+        ei.setTicks(s_kernelName, N * nIterations);
+
+        ei.setStream("a", type, sizeBytes);
+        ei.setLMemLinearWrapped(
+            "a",
+            ZERO,
+            N * size,
+            nIterations * N * size,
+            ZERO);
+        ei.setLMemLinearWrapped(
+            "output",
+            ZERO,
+            N * size,
+            nIterations * N * size,
+            ZERO);
+
+        ei.ignoreStream("fromcpu");
+        ei.ignoreStream("tocpu");
+        ei.ignoreLMem("cpu2lmem");
+        ei.ignoreLMem("lmem2cpu");
+        return ei;
+    }
+
+
+    public static void main(String[] args) {
+        DramAccumulatorManager manager = new DramAccumulatorManager(new EngineParameters(args));
+        manager.createSLiCinterface(interfaceDefault());
+        manager.createSLiCinterface(
+            ManagerUtils.interfaceWrite(
+              "write", "fromcpu", "cpu2lmem"));
+        manager.createSLiCinterface(
+            ManagerUtils.interfaceRead(
+              "read", "tocpu", "lmem2cpu"));
+        manager.build();
+    }
+}