Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Spi bus improvement #18

Open
wants to merge 3 commits into
base: main
Choose a base branch
from
Open

Spi bus improvement #18

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
b857653
SpiBus: use syntax closer to cocotb_bus' Bus
Jun 20, 2024
f858a5e
feature: allow miso to be absent from SpiBus
Jun 20, 2024
61c57ec
update tests with new SpiBus syntax
Jun 20, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
23 changes: 15 additions & 8 deletions README.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -39,7 +39,7 @@ The SPI bus signals are bundled together into a `SpiBus` class.
If the port instantiations look like:
```verilog
module my_module(
input wire sclk,
input wire sclk,
input wire mosi,
output wire miso,
input wire cs, // active-low
Expand All @@ -54,7 +54,7 @@ spi_bus = SpiBus.from_entity(dut)
If there is some prefix, the `from_prefix` class method may be used:
```verilog
module my_module(
input wire spi0_sclk,
input wire spi0_sclk,
input wire spi0_mosi,
output wire spi0_miso,
input wire spi0_cs, // active-low
Expand All @@ -64,17 +64,24 @@ module my_module(
spi_bus = SpiBus.from_prefix(dut, "spi0")
```

If the chip select has been renamed for clarity:
If some signals do not conform to the expected naming scheme, it is possible to use the `[cocotb_bus](https://cocotb-bus.readthedocs.io/en/latest/library_reference.html#cocotb_bus.bus.Bus)` syntax:
```verilog
module my_module(
input wire spi0_sclk,
input wire spi0_mosi,
output wire spi0_miso,
input wire spi0_ncs, // active-low
input wire spi0_A_sclkxDI,
input wire spi0_B_mosixDI,
output wire spi0_C_misoxDO,
input wire spi0_D_ncsxDI, // active-low
)
```
```python
spi_bus = SpiBus.from_prefix(dut, "spi0", cs_name="ncs")
spi_bus = SpiBus(entity = dut,
name = "spi0",
signals = {
'sclk' : 'A_sclkxDI',
'mosi' : 'B_mosixDI',
'miso' : 'C_misoxDO',
'cs' : 'D_ncsxDI'
})
```

### SPI Config
Expand Down
25 changes: 17 additions & 8 deletions cocotbext/spi/spi.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@
from typing import Tuple

import cocotb
from cocotb.binary import BinaryValue
from cocotb.clock import BaseClock
from cocotb.triggers import Edge
from cocotb.triggers import Event
Expand All @@ -24,12 +25,12 @@


class SpiBus(Bus):
_signals = ['sclk', 'mosi', 'miso', 'cs']

def __init__(self, entity=None, prefix=None, **kwargs):
cs_name = kwargs.pop('cs_name', 'cs')
signals = dict(zip(self._signals, self._signals[0:3] + [cs_name]))
super().__init__(entity, prefix, signals, optional_signals=[], **kwargs)
_signals = {
'sclk' : 'sclk',
'mosi' : 'mosi',
'miso' : 'miso',
'cs' : 'cs'
}

@classmethod
def from_entity(cls, entity, **kwargs):
Expand Down Expand Up @@ -60,9 +61,13 @@ def __init__(self, bus: SpiBus, config: SpiConfig) -> None:
# spi signals
self._sclk = bus.sclk
self._mosi = bus.mosi
self._miso = bus.miso
self._cs = bus.cs

if hasattr(bus, 'miso'):
self._miso = bus.miso
else:
self._miso = BinaryValue()

# size of a transfer
self._config = config

Expand Down Expand Up @@ -236,9 +241,13 @@ def __init__(self, bus: SpiBus):

self._sclk = bus.sclk
self._mosi = bus.mosi
self._miso = bus.miso
self._cs = bus.cs

if hasattr(bus, 'miso'):
self._miso = bus.miso
else:
self._miso = BinaryValue()

self._miso.value = self._config.data_output_idle

self.idle = Event()
Expand Down
9 changes: 8 additions & 1 deletion tests/spi/test_spi.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,14 @@ def __init__(self, dut, word_width, spi_mode, msb_first, ignore_rx_value):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)

self.bus = SpiBus.from_entity(dut, cs_name="ncs")
self.bus = SpiBus(entity = dut,
name = None,
signals = {
'sclk' : 'sclk',
'miso' : 'miso',
'mosi' : 'mosi',
'cs' : "ncs"
})

self.config = SpiConfig(
word_width=word_width,
Expand Down
9 changes: 8 additions & 1 deletion tests/spi_devices/ADI/adxl345/test_adxl345.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,14 @@ def __init__(self, dut):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)

self.bus = SpiBus.from_entity(dut, cs_name="ncs")
self.bus = SpiBus(entity = dut,
name = None,
signals = {
'sclk' : 'sclk',
'miso' : 'miso',
'mosi' : 'mosi',
'cs' : "ncs"
})

self.config = SpiConfig(
word_width=8,
Expand Down
9 changes: 8 additions & 1 deletion tests/spi_devices/TI/ads8028/test_ads8028.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,14 @@ def __init__(self, dut):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)

self.bus = SpiBus.from_entity(dut, cs_name="ncs")
self.bus = SpiBus(entity = dut,
name = None,
signals = {
'sclk' : 'sclk',
'miso' : 'miso',
'mosi' : 'mosi',
'cs' : "ncs"
})

self.config = SpiConfig(
word_width=16,
Expand Down
9 changes: 8 additions & 1 deletion tests/spi_devices/TI/drv8304/test_drv8304.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,14 @@ def __init__(self, dut):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)

self.bus = SpiBus.from_entity(dut, cs_name="ncs")
self.bus = SpiBus(entity = dut,
name = None,
signals = {
'sclk' : 'sclk',
'miso' : 'miso',
'mosi' : 'mosi',
'cs' : "ncs"
})

self.config = SpiConfig(
word_width=16,
Expand Down
9 changes: 8 additions & 1 deletion tests/spi_devices/Trinamic/tmc4671/test_tmc4671.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,14 @@ def __init__(self, dut):
self.log = logging.getLogger("cocotb.tb")
self.log.setLevel(logging.DEBUG)

self.bus = SpiBus.from_entity(dut, cs_name="ncs")
self.bus = SpiBus(entity = dut,
name = None,
signals = {
'sclk' : 'sclk',
'miso' : 'miso',
'mosi' : 'mosi',
'cs' : "ncs"
})

self.config = SpiConfig(
word_width=40,
Expand Down
Loading