riscv: telink: add compile support for tl3218x .

- fix retention ram. Signed-off-by: Haiwen Xia <[email protected]>
s07641069 · Jan 13, 2025 · 8a6ad65 · 8a6ad65
1 parent 130ab82
commit 8a6ad65
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Showing 4 changed files with 5 additions and 21 deletions.
diff --git a/.github/workflows/chef.yaml b/.github/workflows/chef.yaml
@@ -111,7 +111,7 @@ jobs:
                 platform: telink
             - name: Update Zephyr to specific revision (for developers purpose)
               shell: bash
-              run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py origin/develop_customer"
+              run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py origin/develop_customer_fix_retention"
             - name: CI Examples Telink
               shell: bash
               run: |

diff --git a/.github/workflows/examples-telink.yaml b/.github/workflows/examples-telink.yaml
@@ -58,7 +58,7 @@ jobs:
                 gh-context: ${{ toJson(github) }}
 
             - name: Update Zephyr to specific revision (for developers purpose)
-              run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py origin/develop_customer"
+              run: scripts/run_in_build_env.sh "python3 scripts/tools/telink/update_zephyr.py origin/develop_customer_fix_retention"
 
             - name: Build example Telink (B92 retention) Air Quality Sensor App
               # Run test for master and s07641069 PRs

diff --git a/config/telink/chip-module/Kconfig.defaults b/config/telink/chip-module/Kconfig.defaults
@@ -84,8 +84,7 @@ config HEAP_MEM_POOL_SIZE
 
 # need to enlarge to 21000 , to pass TC_RR_1.1
 config COMMON_LIBC_MALLOC_ARENA_SIZE
-    default 14336 if SOC_SERIES_RISCV_TELINK_B9X_RETENTION
-    default 13824 if SOC_RISCV_TELINK_TL321X && SOC_SERIES_RISCV_TELINK_TLX_RETENTION
+    default 21000 if SOC_RISCV_TELINK_TL321X || SOC_SERIES_RISCV_TELINK_B9X_RETENTION
     default 12288
 
 config NET_IPV6_MLD
@@ -167,8 +166,7 @@ config BT_GATT_CACHING
 #endif
 
 config BT_RX_STACK_SIZE
-    default 1352 if BT_B9X
-    default 1010 if BT_TLX
+    default 1352 if BT_B9X || BT_TLX
     default 2048 if BT_W91
 
 config BT_HCI_TX_STACK_SIZE

diff --git a/src/platform/telink/SystemPlatformConfig.h b/src/platform/telink/SystemPlatformConfig.h
@@ -44,20 +44,10 @@ struct ChipDeviceEvent;
 #define CHIP_SYSTEM_CONFIG_PLATFORM_PROVIDES_TIME 1
 #endif // CHIP_SYSTEM_CONFIG_USE_POSIX_TIME_FUNCTS
 
-#if defined CONFIG_SOC_RISCV_TELINK_TL321X || defined CONFIG_SOC_SERIES_RISCV_TELINK_B9X_RETENTION
-#if defined CONFIG_IEEE802154_TLX_OPTIMIZATION && CONFIG_IEEE802154_TLX_OPTIMIZATION
-#define CHIP_SYSTEM_PACKETBUFFER_FROM_CHIP_HEAP 0
-#define CHIP_SYSTEM_PACKETBUFFER_FROM_CHIP_POOL 1
-#else /* !CONFIG_IEEE802154_TLX_OPTIMIZATION */
+#if defined(CONFIG_SOC_RISCV_TELINK_TL321X) || defined(CONFIG_SOC_SERIES_RISCV_TELINK_B9X_RETENTION)
 #define CHIP_SYSTEM_PACKETBUFFER_FROM_CHIP_HEAP 1
 #define CHIP_SYSTEM_PACKETBUFFER_FROM_CHIP_POOL 0
-#endif /* CONFIG_IEEE802154_TLX_OPTIMIZATION */
 #define CHIP_SYSTEM_CONFIG_POOL_USE_HEAP 1
-#endif
-
-#if defined CONFIG_SOC_RISCV_TELINK_TL321X
-#define CHIP_SYSTEM_CONFIG_PACKETBUFFER_CAPACITY_MAX 1024
-#elif defined CONFIG_SOC_SERIES_RISCV_TELINK_B9X_RETENTION
 #define CHIP_SYSTEM_CONFIG_PACKETBUFFER_CAPACITY_MAX 1280
 #endif
 
@@ -66,11 +56,7 @@ struct ChipDeviceEvent;
 
 // Reduce packet buffer pool size (default 15) to reduce ram consumption
 #if defined CONFIG_PM || defined CONFIG_SOC_RISCV_TELINK_TL321X
-#if defined CONFIG_IEEE802154_TLX_OPTIMIZATION && CONFIG_IEEE802154_TLX_OPTIMIZATION
-#define CHIP_SYSTEM_CONFIG_PACKETBUFFER_POOL_SIZE 6
-#else /* !CONFIG_IEEE802154_TLX_OPTIMIZATION */
 #define CHIP_SYSTEM_CONFIG_PACKETBUFFER_POOL_SIZE 0
-#endif /* CONFIG_IEEE802154_TLX_OPTIMIZATION */
 #else
 #define CHIP_SYSTEM_CONFIG_PACKETBUFFER_POOL_SIZE 8
 #endif