[AArch64][SVE] Asm: Support for (saturating) vector INC/DEC instructi…

…ons. Increment/decrement vector by multiple of predicate constraint element count. The variants added by this patch are: - INCH, INCW, INC and (saturating): - SQINCH, SQINCW, SQINCD - UQINCH, UQINCW, UQINCW - SQDECH, SQINCW, SQINCD - UQDECH, UQINCW, UQINCW For example: incw z0.s, all, mul #4 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@336090 91177308-0d34-0410-b5e6-96231b3b80d8
rust-lang · Jul 2, 2018 · fe476f5 · fe476f5
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diff --git a/lib/Target/AArch64/AArch64SVEInstrInfo.td b/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -574,6 +574,25 @@ let Predicates = [HasSVE] in {
   defm SQDECD_XPiI   : sve_int_pred_pattern_b_x64<0b11110, "sqdecd">;
   defm UQDECD_XPiI   : sve_int_pred_pattern_b_x64<0b11111, "uqdecd">;
 
+  defm SQINCH_ZPiI : sve_int_countvlv<0b01000, "sqinch", ZPR16>;
+  defm UQINCH_ZPiI : sve_int_countvlv<0b01001, "uqinch", ZPR16>;
+  defm SQDECH_ZPiI : sve_int_countvlv<0b01010, "sqdech", ZPR16>;
+  defm UQDECH_ZPiI : sve_int_countvlv<0b01011, "uqdech", ZPR16>;
+  defm INCH_ZPiI   : sve_int_countvlv<0b01100, "inch",   ZPR16>;
+  defm DECH_ZPiI   : sve_int_countvlv<0b01101, "dech",   ZPR16>;
+  defm SQINCW_ZPiI : sve_int_countvlv<0b10000, "sqincw", ZPR32>;
+  defm UQINCW_ZPiI : sve_int_countvlv<0b10001, "uqincw", ZPR32>;
+  defm SQDECW_ZPiI : sve_int_countvlv<0b10010, "sqdecw", ZPR32>;
+  defm UQDECW_ZPiI : sve_int_countvlv<0b10011, "uqdecw", ZPR32>;
+  defm INCW_ZPiI   : sve_int_countvlv<0b10100, "incw",   ZPR32>;
+  defm DECW_ZPiI   : sve_int_countvlv<0b10101, "decw",   ZPR32>;
+  defm SQINCD_ZPiI : sve_int_countvlv<0b11000, "sqincd", ZPR64>;
+  defm UQINCD_ZPiI : sve_int_countvlv<0b11001, "uqincd", ZPR64>;
+  defm SQDECD_ZPiI : sve_int_countvlv<0b11010, "sqdecd", ZPR64>;
+  defm UQDECD_ZPiI : sve_int_countvlv<0b11011, "uqdecd", ZPR64>;
+  defm INCD_ZPiI   : sve_int_countvlv<0b11100, "incd",   ZPR64>;
+  defm DECD_ZPiI   : sve_int_countvlv<0b11101, "decd",   ZPR64>;
+
   defm INDEX_RR : sve_int_index_rr<"index">;
   defm INDEX_IR : sve_int_index_ir<"index">;
   defm INDEX_RI : sve_int_index_ri<"index">;

diff --git a/lib/Target/AArch64/SVEInstrFormats.td b/lib/Target/AArch64/SVEInstrFormats.td
@@ -285,6 +285,36 @@ let Predicates = [HasSVE] in {
 // SVE Element Count Group
 //===----------------------------------------------------------------------===//
 
+class sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty>
+: I<(outs zprty:$Zdn), (ins zprty:$_Zdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
+  asm, "\t$Zdn, $pattern, mul $imm4",
+  "",
+  []>, Sched<[]> {
+  bits<5> Zdn;
+  bits<5> pattern;
+  bits<4> imm4;
+  let Inst{31-24} = 0b00000100;
+  let Inst{23-22} = opc{4-3};
+  let Inst{21}    = 0b1;
+  let Inst{20}    = opc{2};
+  let Inst{19-16} = imm4;
+  let Inst{15-12} = 0b1100;
+  let Inst{11-10} = opc{1-0};
+  let Inst{9-5}   = pattern;
+  let Inst{4-0}   = Zdn;
+
+  let Constraints = "$Zdn = $_Zdn";
+}
+
+multiclass sve_int_countvlv<bits<5> opc, string asm, ZPRRegOp zprty> {
+  def NAME : sve_int_countvlv<opc, asm, zprty>;
+
+  def : InstAlias<asm # "\t$Zdn, $pattern",
+                  (!cast<Instruction>(NAME) zprty:$Zdn, sve_pred_enum:$pattern, 1), 1>;
+  def : InstAlias<asm # "\t$Zdn",
+                  (!cast<Instruction>(NAME) zprty:$Zdn, 0b11111, 1), 2>;
+}
+
 class sve_int_pred_pattern_a<bits<3> opc, string asm>
 : I<(outs GPR64:$Rdn), (ins GPR64:$_Rdn, sve_pred_enum:$pattern, sve_incdec_imm:$imm4),
   asm, "\t$Rdn, $pattern, mul $imm4",

diff --git a/test/MC/AArch64/SVE/incb-diagnostics.s b/test/MC/AArch64/SVE/incb-diagnostics.s
@@ -13,6 +13,12 @@ incb sp
 // CHECK-NEXT: incb sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
+// INCB does not have a vector equivalent
+incb z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: incb z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
 
 // ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.

diff --git a/test/MC/AArch64/SVE/incd-diagnostics.s b/test/MC/AArch64/SVE/incd-diagnostics.s
@@ -13,6 +13,12 @@ incd sp
 // CHECK-NEXT: incd sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
+// incd requires z0.d
+incd z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: incd z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
 
 // ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.

diff --git a/test/MC/AArch64/SVE/incd.s b/test/MC/AArch64/SVE/incd.s
@@ -7,6 +7,39 @@
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
+// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+
+incd    z0.d
+// CHECK-INST: incd    z0.d
+// CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 f0 04 <unknown>
+
+incd    z0.d, all
+// CHECK-INST: incd    z0.d
+// CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 f0 04 <unknown>
+
+incd    z0.d, all, mul #1
+// CHECK-INST: incd    z0.d
+// CHECK-ENCODING: [0xe0,0xc3,0xf0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 f0 04 <unknown>
+
+incd    z0.d, all, mul #16
+// CHECK-INST: incd    z0.d, all, mul #16
+// CHECK-ENCODING: [0xe0,0xc3,0xff,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 ff 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test scalar form and aliases.
+// ---------------------------------------------------------------------------//
+
 incd    x0
 // CHECK-INST: incd    x0
 // CHECK-ENCODING: [0xe0,0xe3,0xf0,0x04]
@@ -31,6 +64,11 @@ incd    x0, all, mul #16
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 e3 ff 04 <unknown>
 
+
+// ---------------------------------------------------------------------------//
+// Test predicate patterns
+// ---------------------------------------------------------------------------//
+
 incd    x0, pow2
 // CHECK-INST: incd    x0, pow2
 // CHECK-ENCODING: [0x00,0xe0,0xf0,0x04]

diff --git a/test/MC/AArch64/SVE/inch-diagnostics.s b/test/MC/AArch64/SVE/inch-diagnostics.s
@@ -13,6 +13,12 @@ inch sp
 // CHECK-NEXT: inch sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
+// inch requires z0.h
+inch z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: inch z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
 
 // ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.

diff --git a/test/MC/AArch64/SVE/inch.s b/test/MC/AArch64/SVE/inch.s
@@ -7,6 +7,39 @@
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
+// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+
+inch    z0.h
+// CHECK-INST: inch    z0.h
+// CHECK-ENCODING: [0xe0,0xc3,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 70 04 <unknown>
+
+inch    z0.h, all
+// CHECK-INST: inch    z0.h
+// CHECK-ENCODING: [0xe0,0xc3,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 70 04 <unknown>
+
+inch    z0.h, all, mul #1
+// CHECK-INST: inch    z0.h
+// CHECK-ENCODING: [0xe0,0xc3,0x70,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 70 04 <unknown>
+
+inch    z0.h, all, mul #16
+// CHECK-INST: inch    z0.h, all, mul #16
+// CHECK-ENCODING: [0xe0,0xc3,0x7f,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 7f 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test scalar form and aliases.
+// ---------------------------------------------------------------------------//
+
 inch    x0
 // CHECK-INST: inch    x0
 // CHECK-ENCODING: [0xe0,0xe3,0x70,0x04]
@@ -31,6 +64,11 @@ inch    x0, all, mul #16
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 e3 7f 04 <unknown>
 
+
+// ---------------------------------------------------------------------------//
+// Test predicate patterns
+// ---------------------------------------------------------------------------//
+
 inch    x0, pow2
 // CHECK-INST: inch    x0, pow2
 // CHECK-ENCODING: [0x00,0xe0,0x70,0x04]

diff --git a/test/MC/AArch64/SVE/incw-diagnostics.s b/test/MC/AArch64/SVE/incw-diagnostics.s
@@ -13,6 +13,12 @@ incw sp
 // CHECK-NEXT: incw sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
+// incw requires z0.s
+incw z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: incw z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
 
 // ------------------------------------------------------------------------- //
 // Immediate not compatible with encode/decode function.

diff --git a/test/MC/AArch64/SVE/incw.s b/test/MC/AArch64/SVE/incw.s
@@ -7,6 +7,39 @@
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
 // RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 
+// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+
+incw    z0.s
+// CHECK-INST: incw    z0.s
+// CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 b0 04 <unknown>
+
+incw    z0.s, all
+// CHECK-INST: incw    z0.s
+// CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 b0 04 <unknown>
+
+incw    z0.s, all, mul #1
+// CHECK-INST: incw    z0.s
+// CHECK-ENCODING: [0xe0,0xc3,0xb0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 b0 04 <unknown>
+
+incw    z0.s, all, mul #16
+// CHECK-INST: incw    z0.s, all, mul #16
+// CHECK-ENCODING: [0xe0,0xc3,0xbf,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 c3 bf 04 <unknown>
+
+
+// ---------------------------------------------------------------------------//
+// Test scalar form and aliases.
+// ---------------------------------------------------------------------------//
+
 incw    x0
 // CHECK-INST: incw    x0
 // CHECK-ENCODING: [0xe0,0xe3,0xb0,0x04]
@@ -31,6 +64,12 @@ incw    x0, all, mul #16
 // CHECK-ERROR: instruction requires: sve
 // CHECK-UNKNOWN: e0 e3 bf 04 <unknown>
 
+
+// ---------------------------------------------------------------------------//
+// Test predicate patterns
+// ---------------------------------------------------------------------------//
+
+
 incw    x0, pow2
 // CHECK-INST: incw    x0, pow2
 // CHECK-ENCODING: [0x00,0xe0,0xb0,0x04]

diff --git a/test/MC/AArch64/SVE/sqdecb-diagnostics.s b/test/MC/AArch64/SVE/sqdecb-diagnostics.s
@@ -18,6 +18,11 @@ sqdecb sp
 // CHECK-NEXT: sqdecb sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
+sqdecb z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
+// CHECK-NEXT: sqdecb z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
 
 // ------------------------------------------------------------------------- //
 // Operands not matching up

diff --git a/test/MC/AArch64/SVE/sqdecd-diagnostics.s b/test/MC/AArch64/SVE/sqdecd-diagnostics.s
@@ -18,6 +18,11 @@ sqdecd sp
 // CHECK-NEXT: sqdecd sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
+uqdecd z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: uqdecd z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
 
 // ------------------------------------------------------------------------- //
 // Operands not matching up

diff --git a/test/MC/AArch64/SVE/sqdecd.s b/test/MC/AArch64/SVE/sqdecd.s
@@ -77,6 +77,46 @@ sqdecd  x0, w0, pow2, mul #16
 // CHECK-UNKNOWN: 00 f8 ef 04 <unknown>
 
 
+// ---------------------------------------------------------------------------//
+// Test vector form and aliases.
+// ---------------------------------------------------------------------------//
+sqdecd  z0.d
+// CHECK-INST: sqdecd  z0.d
+// CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cb e0 04 <unknown>
+
+sqdecd  z0.d, all
+// CHECK-INST: sqdecd  z0.d
+// CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cb e0 04 <unknown>
+
+sqdecd  z0.d, all, mul #1
+// CHECK-INST: sqdecd  z0.d
+// CHECK-ENCODING: [0xe0,0xcb,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cb e0 04 <unknown>
+
+sqdecd  z0.d, all, mul #16
+// CHECK-INST: sqdecd  z0.d, all, mul #16
+// CHECK-ENCODING: [0xe0,0xcb,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: e0 cb ef 04 <unknown>
+
+sqdecd  z0.d, pow2
+// CHECK-INST: sqdecd  z0.d, pow2
+// CHECK-ENCODING: [0x00,0xc8,0xe0,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c8 e0 04 <unknown>
+
+sqdecd  z0.d, pow2, mul #16
+// CHECK-INST: sqdecd  z0.d, pow2, mul #16
+// CHECK-ENCODING: [0x00,0xc8,0xef,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 c8 ef 04 <unknown>
+
+
 // ---------------------------------------------------------------------------//
 // Test all patterns for 64-bit form
 // ---------------------------------------------------------------------------//

diff --git a/test/MC/AArch64/SVE/sqdech-diagnostics.s b/test/MC/AArch64/SVE/sqdech-diagnostics.s
@@ -18,6 +18,11 @@ sqdech sp
 // CHECK-NEXT: sqdech sp
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
+sqdech z0.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sqdech z0.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
 
 // ------------------------------------------------------------------------- //
 // Operands not matching up