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[AArch64/ARM64] Update to Capstone v6/auto-sync #3785

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[AArch64/ARM64] Update to Capstone v6/auto-sync #3785

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7399e86
[AArch64 CS v6 BEGIN] Change subproject config to use cs-auto-sync-aa…
Rot127 Aug 24, 2023
4685687
Replace ARM64 with version sensitive macros.
Rot127 Aug 26, 2023
9cecbd0
Exclude alias if CS version >= 6
Rot127 Aug 26, 2023
e94c736
Update access to writeback member
Rot127 Aug 26, 2023
a76f93e
Exclude instr alias from inclusion
Rot127 Aug 26, 2023
d9b45ab
Update memory operand printing to json.
Rot127 Aug 26, 2023
b5aa35d
Enable real instr. detail only for AArch64
Rot127 Aug 26, 2023
2e80b0a
Set correct arch name in meson.build for CS
Rot127 Aug 26, 2023
d71d413
Fix U/SBFM instructions and their alias.
Rot127 Aug 27, 2023
d50da84
Mark parameters with RZ_OUt/BORROW
Rot127 Aug 27, 2023
f9238f8
Optimize register extension to skip some, if the width already matches.
Rot127 Aug 27, 2023
9f244a4
Adapt width and lsb of U/SBFM alias instructions (ImmR and ImmS are f…
Rot127 Aug 28, 2023
d3d8deb
Fix tests correct semantic buy bad syntax
Rot127 Aug 28, 2023
b107317
Pass alias MOV instructions to mov()
Rot127 Aug 28, 2023
8162335
Handle CSET and CSETM alias
Rot127 Aug 28, 2023
ef320b2
Fix lsl, lsr and asr by handling them as alias.
Rot127 Aug 28, 2023
e32e8cb
Fix mov alias.
Rot127 Aug 29, 2023
6234e72
Handle TST alias
Rot127 Aug 29, 2023
f6ad586
Fix CNEG, CINV alias
Rot127 Aug 29, 2023
9d58e11
Fix bfi and bfxil alias.
Rot127 Aug 29, 2023
48ad5f1
Fix sign extensions.
Rot127 Aug 29, 2023
7a5a394
Fix compare instructions.
Rot127 Aug 29, 2023
09a453d
Fix NEG, NGC, NGCS, NEGS, MVN
Rot127 Aug 29, 2023
9d63a13
Fix CINC
Rot127 Aug 29, 2023
adb9e7c
Fix multiply instructions.
Rot127 Aug 29, 2023
dec513d
Fix ROR
Rot127 Aug 29, 2023
8bb6c89
Run clang-format
Rot127 Aug 29, 2023
9bfc458
Handle CMP for ESIL
Rot127 Aug 30, 2023
5b3fba4
Handle new position of memory disponents of post index operands.
Rot127 Aug 30, 2023
f2724f2
Fix post-index operations.
Rot127 Aug 30, 2023
55d543c
Add missing writeback checks for Post and preindex
Rot127 Aug 30, 2023
89e935a
Handle UBFM and SBFM alias
Rot127 Aug 30, 2023
4a46cb6
Handl BFM alias
Rot127 Aug 30, 2023
e825eb1
Handle CMP, CSET and CINC alias
Rot127 Aug 30, 2023
bc1edfa
Update meson file of for cs-aarch64 branch
Rot127 Oct 11, 2023
34b5697
Fix asm tests. Use reg alias now.
Rot127 Oct 11, 2023
2198316
Fix condition confusion and incorrect operand usage.
Rot127 Oct 12, 2023
4e60720
Fix plf test.
Rot127 Oct 13, 2023
9aef59c
Run clang-format
Rot127 Oct 13, 2023
fb94179
Use register alias in tests
Rot127 Oct 13, 2023
1a91862
Add support for fp and lr reg alias assembly.
Rot127 Oct 14, 2023
28c9417
Use reg alias in test
Rot127 Oct 14, 2023
da03e5b
Rename cond tranlate functions r2 -> rz
Rot127 Oct 14, 2023
6d910f5
Fix condition check which assume 0 == invalid.
Rot127 Oct 14, 2023
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31 changes: 20 additions & 11 deletions librz/analysis/arch/arm/arm_accessors64.h
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Original file line number Diff line number Diff line change
Expand Up @@ -9,21 +9,30 @@

#include <capstone/capstone.h>

#define IMM64(x) (ut64)(insn->detail->arm64.operands[x].imm)
#define INSOP64(x) insn->detail->arm64.operands[x]
#define IMM64(x) (ut64)(insn->detail->CS_aarch64().operands[x].imm)
#define INSOP64(x) insn->detail->CS_aarch64().operands[x]

#define REGID64(x) insn->detail->arm64.operands[x].reg
#define REGBASE64(x) insn->detail->arm64.operands[x].mem.base
#define REGID64(x) insn->detail->CS_aarch64().operands[x].reg
#define REGBASE64(x) insn->detail->CS_aarch64().operands[x].mem.base
// s/index/base|reg/
#define HASMEMINDEX64(x) (insn->detail->arm64.operands[x].mem.index != ARM64_REG_INVALID)
#define MEMDISP64(x) (ut64) insn->detail->arm64.operands[x].mem.disp
#define ISIMM64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_IMM)
#define ISREG64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_REG)
#define ISMEM64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_MEM)
#define HASMEMINDEX64(x) (insn->detail->CS_aarch64().operands[x].mem.index != CS_AARCH64(_REG_INVALID))
#define MEMDISP64(x) (ut64) insn->detail->CS_aarch64().operands[x].mem.disp
#define ISIMM64(x) (insn->detail->CS_aarch64().operands[x].type == CS_AARCH64(_OP_IMM))
#define ISREG64(x) (insn->detail->CS_aarch64().operands[x].type == CS_AARCH64(_OP_REG))
#define ISMEM64(x) (insn->detail->CS_aarch64().operands[x].type == CS_AARCH64(_OP_MEM))

#define LSHIFT2_64(x) insn->detail->arm64.operands[x].shift.value
#define OPCOUNT64() insn->detail->arm64.op_count
#define LSHIFT2_64(x) insn->detail->CS_aarch64().operands[x].shift.value
#define OPCOUNT64() insn->detail->CS_aarch64().op_count

#if CS_NEXT_VERSION < 6
#define ISWRITEBACK64() (insn->detail->arm64.writeback == true)
#else
#define ISWRITEBACK64() (insn->detail->writeback == true)
#endif
#if CS_NEXT_VERSION < 6
#define ISPREINDEX64() (((OPCOUNT64() == 2) && (ISMEM64(1)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 3) && (ISMEM64(2)) && (ISWRITEBACK64())))
#define ISPOSTINDEX64() (((OPCOUNT64() == 3) && (ISIMM64(2)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 4) && (ISIMM64(3)) && (ISWRITEBACK64())))
#else
#define ISPREINDEX64() (!insn->detail->CS_aarch64().post_index && ISWRITEBACK64())
#define ISPOSTINDEX64() (insn->detail->CS_aarch64().post_index && ISWRITEBACK64())
#endif
2 changes: 1 addition & 1 deletion librz/analysis/arch/arm/arm_cs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, ARMCC_CondCode
#else
RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, arm_cc cond_type);
#endif
RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, arm64_cc cond_type);
RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, CS_aarch64_cc() cond_type);

RZ_IPI RzILOpEffect *rz_arm_cs_32_il(csh *handle, cs_insn *insn, bool thumb);
RZ_IPI RzAnalysisILConfig *rz_arm_cs_32_il_config(bool big_endian);
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