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[ARM] Update to Capstone v6/auto-sync #3591

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[ARM] Update to Capstone v6/auto-sync #3591

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b2c7443
[REVERT ME] Add auto-sync Capstone
Rot127 Jun 19, 2023
4032495
Fix ARM identifiers and API changes.
Rot127 Jun 19, 2023
d163d67
Add auto-sync packagefile
Rot127 Jun 19, 2023
931474e
Rename registers
Rot127 Jun 19, 2023
5511a7b
Set option for CS register alias.
Rot127 Jun 21, 2023
e4017f8
Fix: Shift amounts are always decimal.
Rot127 Jun 21, 2023
aea3728
Remove code which handles fixed CS issue.
Rot127 Jun 26, 2023
c8b98c8
Use mem disp which is a member of the member operand.
Rot127 Jun 26, 2023
6c224cc
Get register and imm memory disponent.
Rot127 Jun 26, 2023
a239afc
Remove duplicate extension
Rot127 Jun 29, 2023
280582e
Check for subtracted flag.
Rot127 Jun 29, 2023
14d2717
Determine post writeback by CS em operand flag.
Rot127 Jul 1, 2023
26c5e96
Add VPOP and VPUSH again.
Rot127 Jul 2, 2023
3de62b1
Check for subtracted flag if disp is added to PC
Rot127 Jul 3, 2023
648e818
Fix hex <-> decimal tests and off by one
Rot127 Jul 3, 2023
61f059e
Print immediates ins signed form as LLVM does.
Rot127 Jul 3, 2023
c55f1b1
Fix tests wit equivalent results
Rot127 Jul 3, 2023
fd08217
Revert use of subtracted flag and move it into the macro
Rot127 Jul 4, 2023
2b87d56
Check for VPT blocks.
Rot127 Jul 4, 2023
94d9b5b
Fix more incorrect usages of mem disponents
Rot127 Jul 5, 2023
36d6e2a
Fix restoring of condition codes.
Rot127 Jul 5, 2023
a73e925
Test for shifting via registers.
Rot127 Jul 5, 2023
d78a5bd
Fix: mem index is no longer its own operand.
Rot127 Jul 5, 2023
1fef4fa
Update ids for new ones
Rot127 Jul 5, 2023
119f871
Fix another memdisp post_index bug
Rot127 Jul 6, 2023
725755e
Formatting
Rot127 Jul 6, 2023
d97aa4b
Another post_index
Rot127 Jul 6, 2023
bc08e63
Fix 8 byte stores.
Rot127 Jul 6, 2023
2a4cf01
Add flag checking for MOV with shifts.
Rot127 Jul 6, 2023
6d6a048
Revert "[REVERT ME] Add auto-sync Capstone"
Rot127 Jul 20, 2023
be42601
Remove capstone-auto-sync subproject and replace with next
Rot127 Jul 20, 2023
7781cec
Fix rebase mistakes
Rot127 Jul 20, 2023
3c5fc45
Check for NEON features.
Rot127 Jul 20, 2023
d51cf41
Fix tests where ldr was replaced with pop
Rot127 Jul 21, 2023
7229d5a
Fix postindex 8byte store
Rot127 Jul 21, 2023
cbe6366
Remove unreachable code for ESIL LDR.
Rot127 Jul 21, 2023
17ca894
Fix flag check/set of mov instructions with shift.
Rot127 Jul 21, 2023
2c0d744
Check for subtracted flag of mem.disp.
Rot127 Jul 21, 2023
a0e905f
Use macro for disp access
Rot127 Jul 22, 2023
7fc913c
Fix function variable recognition.
Rot127 Jul 22, 2023
9c220a0
Fix json tests
Rot127 Jul 22, 2023
61f65fe
Fix new id
Rot127 Jul 22, 2023
8c039b4
Fix post-index ldrd esil instructions
Rot127 Jul 22, 2023
75a7ff2
Fix ARM64 tests by separating their esil condition code.
Rot127 Jul 22, 2023
837dcb5
Fix shift of post index stores
Rot127 Jul 22, 2023
f7d50db
Fix more post index memory instructions.
Rot127 Jul 22, 2023
5afd6f8
Fix invalid variable recognition.
Rot127 Jul 22, 2023
50bc8b3
Use https://github.com/capstone-engine/capstone/pull/2122 for better …
Rot127 Jul 23, 2023
ed2a3dd
Distinguish between 32 and 64bit cc check.
Rot127 Jul 23, 2023
18dc5d7
Check for CS API version >5
Rot127 Jul 23, 2023
23c371c
Check for CS_NEXT_VERSION instead of CS_API_MAJOR.
Rot127 Jul 24, 2023
3341388
Fix VSTn and VLDn instructions to use corrected memory operands.
Rot127 Sep 7, 2023
327ef81
Fix incorrect tests with missing writeback due to missing post-index …
Rot127 Sep 7, 2023
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11 changes: 7 additions & 4 deletions librz/analysis/arch/arm/arm_accessors32.h
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Original file line number Diff line number Diff line change
Expand Up @@ -17,9 +17,11 @@
// s/index/base|reg/
#define HASMEMINDEX(x) (insn->detail->arm.operands[x].mem.index != ARM_REG_INVALID)
#define ISMEMINDEXSUB(x) insn->detail->arm.operands[x].subtracted
#define MEMDISP(x) insn->detail->arm.operands[x].mem.disp
#define MEMDISP(x) (ISMEMINDEXSUB(x) ? -insn->detail->arm.operands[x].mem.disp : insn->detail->arm.operands[x].mem.disp)
#define MEMDISP_BV(x) (HASMEMINDEX(x) ? REG_VAL(insn->detail->arm.operands[x].mem.index) : U32(MEMDISP(x)))
#define ISIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_IMM || insn->detail->arm.operands[x].type == ARM_OP_FP)
#define ISREG(x) (insn->detail->arm.operands[x].type == ARM_OP_REG)
#define ISPSRFLAGS(x) (insn->detail->arm.operands[x].type == ARM_OP_CPSR || insn->detail->arm.operands[x].type == ARM_OP_SPSR)
#define ISMEM(x) (insn->detail->arm.operands[x].type == ARM_OP_MEM)
#define ISFPIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_FP)

Expand All @@ -38,6 +40,7 @@
SHIFTTYPE(x) == ARM_SFT_RRX_REG)
#define SHIFTVALUE(x) insn->detail->arm.operands[x].shift.value

#define ISWRITEBACK32() insn->detail->arm.writeback
#define ISPREINDEX32() (((OPCOUNT() == 2) && (ISMEM(1)) && (ISWRITEBACK32())) || ((OPCOUNT() == 3) && (ISMEM(2)) && (ISWRITEBACK32())))
#define ISPOSTINDEX32() (((OPCOUNT() == 3) && (ISIMM(2) || ISREG(2)) && (ISWRITEBACK32())) || ((OPCOUNT() == 4) && (ISIMM(3) || ISREG(3)) && (ISWRITEBACK32())))
#define ISPOSTINDEX() insn->detail->arm.post_index
#define ISWRITEBACK32() insn->detail->writeback
#define ISPREINDEX32() (((OPCOUNT() == 2) && (ISMEM(1)) && (ISWRITEBACK32()) && (!ISPOSTINDEX())) || \
((OPCOUNT() == 3) && (ISMEM(2)) && (ISWRITEBACK32()) && (!ISPOSTINDEX())))
5 changes: 4 additions & 1 deletion librz/analysis/arch/arm/arm_cs.h
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,10 @@
RZ_IPI int rz_arm_cs_analysis_op_32_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn, bool thumb);
RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn);

RZ_IPI const char *rz_arm_cs_esil_prefix_cond(RzAnalysisOp *op, int cond_type);
RZ_IPI bool rz_arm_cs_is_group_member(const cs_insn *insn, arm_insn_group feature);

RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, ARMCC_CondCodes cond_type);
RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, arm64_cc cond_type);

RZ_IPI RzILOpEffect *rz_arm_cs_32_il(csh *handle, cs_insn *insn, bool thumb);
RZ_IPI RzAnalysisILConfig *rz_arm_cs_32_il_config(bool big_endian);
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