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[ARM] Test Capstone auto-sync #3399

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[ARM] Test Capstone auto-sync #3399

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99b1a76
Capstone auto-sync branch as subprocject.
Rot127 Feb 23, 2023
d5d20b1
Update enum names.
Rot127 Feb 23, 2023
b8d5c0f
Use `auto-sync` capstone branch as default for build.
Rot127 Feb 23, 2023
bf8a67b
Add TODO comment.
Rot127 Feb 27, 2023
ed05be2
Rename register alias to raw name.
Rot127 Feb 28, 2023
5583741
Merge branch 'dev' into dist-cs-auto-sync
Rot127 Apr 5, 2023
5c5f22f
Replace removed enum value.
Rot127 Apr 13, 2023
cf2054a
Capstone auto-sync branch as subprocject.
Rot127 Feb 23, 2023
2ac340d
Update enum names.
Rot127 Feb 23, 2023
2ad90a0
Use `auto-sync` capstone branch as default for build.
Rot127 Feb 23, 2023
f552635
Add TODO comment.
Rot127 Feb 27, 2023
488c406
Rename register alias to raw name.
Rot127 Feb 28, 2023
87bffaa
Replace removed enum value.
Rot127 Apr 13, 2023
e140a62
Merge branch 'dist-cs-auto-sync' of github.com:Rot127/rizin into dist…
Rot127 May 6, 2023
35dee07
Fix build errors for recent CS auto-sync.
Rot127 May 6, 2023
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2 changes: 1 addition & 1 deletion librz/analysis/arch/arm/arm_accessors32.h
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Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,6 @@
#define SHIFTTYPE(x) insn->detail->arm.operands[x].shift.type
#define SHIFTVALUE(x) insn->detail->arm.operands[x].shift.value

#define ISWRITEBACK32() insn->detail->arm.writeback
#define ISWRITEBACK32() insn->detail->writeback
#define ISPREINDEX32() (((OPCOUNT() == 2) && (ISMEM(1)) && (ISWRITEBACK32())) || ((OPCOUNT() == 3) && (ISMEM(2)) && (ISWRITEBACK32())))
#define ISPOSTINDEX32() (((OPCOUNT() == 3) && (ISIMM(2) || ISREG(2)) && (ISWRITEBACK32())) || ((OPCOUNT() == 4) && (ISIMM(3) || ISREG(3)) && (ISWRITEBACK32())))
60 changes: 30 additions & 30 deletions librz/analysis/arch/arm/arm_esil32.c
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Original file line number Diff line number Diff line change
Expand Up @@ -66,65 +66,65 @@ RZ_IPI const char *rz_arm_cs_esil_prefix_cond(RzAnalysisOp *op, int cond_type) {
close_cond[1] = ",}";
int close_type = 0;
switch (cond_type) {
case ARM_CC_EQ:
case ARMCC_EQ:
close_type = 1;
rz_strbuf_setf(&op->esil, "zf,?{,");
break;
case ARM_CC_NE:
case ARMCC_NE:
close_type = 1;
rz_strbuf_setf(&op->esil, "zf,!,?{,");
break;
case ARM_CC_HS:
case ARMCC_HS:
close_type = 1;
rz_strbuf_setf(&op->esil, "cf,?{,");
break;
case ARM_CC_LO:
case ARMCC_LO:
close_type = 1;
rz_strbuf_setf(&op->esil, "cf,!,?{,");
break;
case ARM_CC_MI:
case ARMCC_MI:
close_type = 1;
rz_strbuf_setf(&op->esil, "nf,?{,");
break;
case ARM_CC_PL:
case ARMCC_PL:
close_type = 1;
rz_strbuf_setf(&op->esil, "nf,!,?{,");
break;
case ARM_CC_VS:
case ARMCC_VS:
close_type = 1;
rz_strbuf_setf(&op->esil, "vf,?{,");
break;
case ARM_CC_VC:
case ARMCC_VC:
close_type = 1;
rz_strbuf_setf(&op->esil, "vf,!,?{,");
break;
case ARM_CC_HI:
case ARMCC_HI:
close_type = 1;
rz_strbuf_setf(&op->esil, "cf,zf,!,&,?{,");
break;
case ARM_CC_LS:
case ARMCC_LS:
close_type = 1;
rz_strbuf_setf(&op->esil, "cf,!,zf,|,?{,");
break;
case ARM_CC_GE:
case ARMCC_GE:
close_type = 1;
rz_strbuf_setf(&op->esil, "nf,vf,^,!,?{,");
break;
case ARM_CC_LT:
case ARMCC_LT:
close_type = 1;
rz_strbuf_setf(&op->esil, "nf,vf,^,?{,");
break;
case ARM_CC_GT:
case ARMCC_GT:
// zf == 0 && nf == vf
close_type = 1;
rz_strbuf_setf(&op->esil, "zf,!,nf,vf,^,!,&,?{,");
break;
case ARM_CC_LE:
case ARMCC_LE:
// zf == 1 || nf != vf
close_type = 1;
rz_strbuf_setf(&op->esil, "zf,nf,vf,^,|,?{,");
break;
case ARM_CC_AL:
case ARMCC_AL:
// always executed
break;
default:
Expand Down Expand Up @@ -383,7 +383,7 @@ PUSH { r4, r5, r6, r7, lr }
rz_strbuf_appendf(&op->esil, "%s,%s,%d,+,=[4],",
REG(i), ARG(0), (i + offset) * 4);
}
if (insn->detail->arm.writeback == true) { // writeback, reg should be incremented
if (insn->detail->writeback == true) { // writeback, reg should be incremented
rz_strbuf_appendf(&op->esil, "%d,%s,+=,",
direction * (insn->detail->arm.op_count - 1) * 4, ARG(0));
}
Expand All @@ -398,7 +398,7 @@ PUSH { r4, r5, r6, r7, lr }
width += REGSIZE32(i);
}
// increment if writeback
if (insn->detail->arm.writeback) {
if (insn->detail->writeback) {
rz_strbuf_appendf(&op->esil, "%d,%s,+=,", width, ARG(0));
}
break;
Expand All @@ -422,7 +422,7 @@ PUSH { r4, r5, r6, r7, lr }
width += REGSIZE32(i);
}
// increment if writeback
if (insn->detail->arm.writeback) {
if (insn->detail->writeback) {
rz_strbuf_appendf(&op->esil, "%d,%s,+=,", width, ARG(0));
}
break;
Expand Down Expand Up @@ -481,7 +481,7 @@ r6,r5,r4,3,sp,[*],12,sp,+=
for (i = 1; i < insn->detail->arm.op_count; i++) {
rz_strbuf_appendf(&op->esil, "%s,%d,+,[4],%s,=,", ARG(0), (i + offset) * 4, REG(i));
}
if (insn->detail->arm.writeback) {
if (insn->detail->writeback) {
rz_strbuf_appendf(&op->esil, "%d,%s,+=,",
direction * (insn->detail->arm.op_count - 1) * 4, ARG(0));
}
Expand Down Expand Up @@ -544,7 +544,7 @@ r6,r5,r4,3,sp,[*],12,sp,+=
disp = disp >= 0 ? disp : -disp;
rz_strbuf_appendf(&op->esil, "%s,0x%x,%s,%c,0xffffffff,&,=[%d]",
REG(0), disp, MEMBASE(1), sign, str_ldr_bytes);
if (insn->detail->arm.writeback) {
if (insn->detail->writeback) {
rz_strbuf_appendf(&op->esil, ",%d,%s,%c,%s,=",
disp, MEMBASE(1), sign, MEMBASE(1));
}
Expand All @@ -555,31 +555,31 @@ r6,r5,r4,3,sp,[*],12,sp,+=
case ARM_SFT_LSL:
rz_strbuf_appendf(&op->esil, "%s,%s,%d,%s,<<,+,0xffffffff,&,=[%d]",
REG(0), MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), str_ldr_bytes);
if (insn->detail->arm.writeback) { // e.g. 'str r2, [r3, r1, lsl 4]!'
if (insn->detail->writeback) { // e.g. 'str r2, [r3, r1, lsl 4]!'
rz_strbuf_appendf(&op->esil, ",%s,%d,%s,<<,+,%s,=",
MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), MEMBASE(1));
}
break;
case ARM_SFT_LSR:
rz_strbuf_appendf(&op->esil, "%s,%s,%d,%s,>>,+,0xffffffff,&,=[%d]",
REG(0), MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), str_ldr_bytes);
if (insn->detail->arm.writeback) {
if (insn->detail->writeback) {
rz_strbuf_appendf(&op->esil, ",%s,%d,%s,>>,+,%s,=",
MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), MEMBASE(1));
}
break;
case ARM_SFT_ASR:
rz_strbuf_appendf(&op->esil, "%s,%s,%d,%s,>>>>,+,0xffffffff,&,=[%d]",
REG(0), MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), str_ldr_bytes);
if (insn->detail->arm.writeback) {
if (insn->detail->writeback) {
rz_strbuf_appendf(&op->esil, ",%s,%d,%s,>>>>,+,%s,=",
MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), MEMBASE(1));
}
break;
case ARM_SFT_ROR:
rz_strbuf_appendf(&op->esil, "%s,%s,%d,%s,>>>,+,0xffffffff,&,=[%d]",
REG(0), MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), str_ldr_bytes);
if (insn->detail->arm.writeback) {
if (insn->detail->writeback) {
rz_strbuf_appendf(&op->esil, ",%s,%d,%s,>>>,+,%s,=",
MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), MEMBASE(1));
}
Expand All @@ -594,7 +594,7 @@ r6,r5,r4,3,sp,[*],12,sp,+=
} else { // No shift
rz_strbuf_appendf(&op->esil, "%s,%s,%s,+,0xffffffff,&,=[%d]",
REG(0), MEMINDEX(1), MEMBASE(1), str_ldr_bytes);
if (insn->detail->arm.writeback) {
if (insn->detail->writeback) {
rz_strbuf_appendf(&op->esil, ",%s,%s,+,%s,=",
MEMINDEX(1), MEMBASE(1), MEMBASE(1));
}
Expand Down Expand Up @@ -644,7 +644,7 @@ r6,r5,r4,3,sp,[*],12,sp,+=
disp = disp >= 0 ? disp : -disp;
rz_strbuf_appendf(&op->esil, "%s,%d,%s,%c,0xffffffff,&,=[4],%s,4,%d,+,%s,%c,0xffffffff,&,=[4]",
REG(0), disp, MEMBASE(2), sign, REG(1), disp, MEMBASE(2), sign);
if (insn->detail->arm.writeback) {
if (insn->detail->writeback) {
rz_strbuf_appendf(&op->esil, ",%d,%s,%c,%s,=",
disp, MEMBASE(2), sign, MEMBASE(2));
}
Expand All @@ -654,7 +654,7 @@ r6,r5,r4,3,sp,[*],12,sp,+=
} else {
rz_strbuf_appendf(&op->esil, "%s,%s,%s,+,0xffffffff,&,=[4],%s,4,%s,+,%s,+,0xffffffff,&,=[4]",
REG(0), MEMINDEX(2), MEMBASE(2), REG(1), MEMINDEX(2), MEMBASE(2));
if (insn->detail->arm.writeback) {
if (insn->detail->writeback) {
rz_strbuf_appendf(&op->esil, ",%s,%s,+,%s,=",
MEMINDEX(2), MEMBASE(2), MEMBASE(2));
}
Expand Down Expand Up @@ -722,7 +722,7 @@ r6,r5,r4,3,sp,[*],12,sp,+=
rz_strbuf_appendf(&op->esil, "%d,%s,+,0xffffffff,&,DUP,[4],%s,=,4,+,[4],%s,=",
MEMDISP(2), MEMBASE(2), REG(0), REG(1));
}
if (insn->detail->arm.writeback) {
if (insn->detail->writeback) {
if (ISPOSTINDEX32()) {
if (ISIMM(3)) {
rz_strbuf_appendf(&op->esil, ",%s,%d,+,%s,=",
Expand Down Expand Up @@ -757,7 +757,7 @@ r6,r5,r4,3,sp,[*],12,sp,+=
rz_strbuf_appendf(&op->esil, "%s,%d,+,[1],%s,=",
MEMBASE(1), MEMDISP(1), REG(0));
}
if (insn->detail->arm.writeback) {
if (insn->detail->writeback) {
if (ISIMM(2)) {
rz_strbuf_appendf(&op->esil, ",%s,%d,+,%s,=",
MEMBASE(1), IMM(2), MEMBASE(1));
Expand Down Expand Up @@ -850,7 +850,7 @@ r6,r5,r4,3,sp,[*],12,sp,+=
rz_strbuf_appendf(&op->esil, "%d,%s,+,0xffffffff,&,[4],0x%x,&,%s,=",
MEMDISP(1), MEMBASE(1), mask, REG(0));
}
if (insn->detail->arm.writeback) {
if (insn->detail->writeback) {
if (ISIMM(2)) {
rz_strbuf_appendf(&op->esil, ",%s,%d,+,%s,=",
MEMBASE(1), IMM(2), MEMBASE(1));
Expand Down
53 changes: 25 additions & 28 deletions librz/analysis/arch/arm/arm_il32.c
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Original file line number Diff line number Diff line change
Expand Up @@ -138,37 +138,37 @@ static RzILOpEffect *write_reg(arm_reg reg, RZ_OWN RZ_NONNULL RzILOpBitVector *v
* IL for arm condition
* unconditional is returned as NULL (rather than true), for simpler code
*/
static RZ_NULLABLE RzILOpBool *cond(arm_cc c) {
static RZ_NULLABLE RzILOpBool *cond(ARMCC_CondCodes c) {
switch (c) {
case ARM_CC_EQ:
case ARMCC_EQ:
return VARG("zf");
case ARM_CC_NE:
case ARMCC_NE:
return INV(VARG("zf"));
case ARM_CC_HS:
case ARMCC_HS:
return VARG("cf");
case ARM_CC_LO:
case ARMCC_LO:
return INV(VARG("cf"));
case ARM_CC_MI:
case ARMCC_MI:
return VARG("nf");
case ARM_CC_PL:
case ARMCC_PL:
return INV(VARG("nf"));
case ARM_CC_VS:
case ARMCC_VS:
return VARG("vf");
case ARM_CC_VC:
case ARMCC_VC:
return INV(VARG("vf"));
case ARM_CC_HI:
case ARMCC_HI:
return AND(VARG("cf"), INV(VARG("zf")));
case ARM_CC_LS:
case ARMCC_LS:
return OR(INV(VARG("cf")), VARG("zf"));
case ARM_CC_GE:
case ARMCC_GE:
return INV(XOR(VARG("nf"), VARG("vf")));
case ARM_CC_LT:
case ARMCC_LT:
return XOR(VARG("nf"), VARG("vf"));
case ARM_CC_GT:
case ARMCC_GT:
return AND(INV(VARG("zf")), INV(XOR(VARG("nf"), VARG("vf"))));
case ARM_CC_LE:
case ARMCC_LE:
return OR(VARG("zf"), XOR(VARG("nf"), VARG("vf")));
case ARM_CC_AL:
case ARMCC_AL:
default:
return NULL;
}
Expand Down Expand Up @@ -578,7 +578,7 @@ static RzILOpEffect *ldr(cs_insn *insn, bool is_thumb) {
if (!addr) {
return NULL;
}
bool writeback = insn->detail->arm.writeback;
bool writeback = insn->detail->writeback;
if (ISIMM(mem_idx + 1)) {
// capstone incorrectly sets writeback to false for e.g. 0400b1e4 ldrt r0, [r1], 4
writeback = true;
Expand Down Expand Up @@ -667,7 +667,7 @@ static RzILOpEffect *str(cs_insn *insn, bool is_thumb) {
if (!addr) {
return NULL;
}
bool writeback = insn->detail->arm.writeback;
bool writeback = insn->detail->writeback;
if (ISIMM(mem_idx + 1)) {
// capstone incorrectly sets writeback to false for e.g. 04b0ade4 strt fp, [sp], 4
writeback = true;
Expand Down Expand Up @@ -969,7 +969,7 @@ static RzILOpEffect *stm(cs_insn *insn, bool is_thumb) {
size_t op_first;
arm_reg ptr_reg;
bool writeback;
if (insn->id == ARM_INS_PUSH || insn->id == ARM_INS_VPUSH) {
if (insn->id == ARM_INS_PUSH) {
op_first = 0;
ptr_reg = ARM_REG_SP;
writeback = true;
Expand All @@ -979,7 +979,7 @@ static RzILOpEffect *stm(cs_insn *insn, bool is_thumb) {
}
op_first = 1;
ptr_reg = REGID(0);
writeback = insn->detail->arm.writeback;
writeback = insn->detail->writeback;
}
size_t op_count = OPCOUNT() - op_first;
if (!op_count) {
Expand All @@ -990,9 +990,9 @@ static RzILOpEffect *stm(cs_insn *insn, bool is_thumb) {
return NULL;
}
bool decrement = insn->id == ARM_INS_STMDA || insn->id == ARM_INS_STMDB || insn->id == ARM_INS_PUSH ||
insn->id == ARM_INS_VSTMDB || insn->id == ARM_INS_VPUSH;
insn->id == ARM_INS_VSTMDB;
bool before = insn->id == ARM_INS_STMDB || insn->id == ARM_INS_PUSH || insn->id == ARM_INS_VSTMDB ||
insn->id == ARM_INS_STMIB || insn->id == ARM_INS_VPUSH;
insn->id == ARM_INS_STMIB;
ut32 regsize = reg_bits(REGID(op_first)) / 8;
RzILOpEffect *eff = NULL;
// build up in reverse order so the result recurses in the second arg of seq (for tail-call optimization)
Expand Down Expand Up @@ -1030,7 +1030,7 @@ static RzILOpEffect *ldm(cs_insn *insn, bool is_thumb) {
size_t op_first;
arm_reg ptr_reg;
bool writeback;
if (insn->id == ARM_INS_POP || insn->id == ARM_INS_VPOP) {
if (insn->id == ARM_INS_POP) {
op_first = 0;
ptr_reg = ARM_REG_SP;
writeback = true;
Expand All @@ -1040,7 +1040,7 @@ static RzILOpEffect *ldm(cs_insn *insn, bool is_thumb) {
}
op_first = 1;
ptr_reg = REGID(0);
writeback = insn->detail->arm.writeback;
writeback = insn->detail->writeback;
}
size_t op_count = OPCOUNT() - op_first;
if (!op_count) {
Expand Down Expand Up @@ -1633,7 +1633,7 @@ static RzILOpEffect *rfe(cs_insn *insn, bool is_thumb) {
RzILOpEffect *wb = NULL;
bool wordhigher = insn->id == ARM_INS_RFEDA || insn->id == ARM_INS_RFEIB;
bool increment = insn->id == ARM_INS_RFEIA || insn->id == ARM_INS_RFEIB;
if (insn->detail->arm.writeback) {
if (insn->detail->writeback) {
wb = write_reg(REGID(0),
increment ? ADD(DUP(base), U32(8)) : SUB(DUP(base), U32(8)));
if (!wb) {
Expand Down Expand Up @@ -2360,7 +2360,6 @@ static RzILOpEffect *il_unconditional(csh *handle, cs_insn *insn, bool is_thumb)
case ARM_INS_PLD:
case ARM_INS_PLDW:
case ARM_INS_PLI:
case ARM_INS_YIELD:
// barriers/synchronization
case ARM_INS_DMB:
case ARM_INS_DSB:
Expand Down Expand Up @@ -2630,11 +2629,9 @@ static RzILOpEffect *il_unconditional(csh *handle, cs_insn *insn, bool is_thumb)
// Advanced SIMD and Floating-point
case ARM_INS_VSTMIA:
case ARM_INS_VSTMDB:
case ARM_INS_VPUSH:
return stm(insn, is_thumb);
case ARM_INS_VLDMIA:
case ARM_INS_VLDMDB:
case ARM_INS_VPOP:
return ldm(insn, is_thumb);
case ARM_INS_VMOV:
return vmov(insn, is_thumb);
Expand Down
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