config work continues.

riscv · Aug 6, 2022 · df115f9 · df115f9
1 parent b77c1b2
commit df115f9
Show file tree

Hide file tree

Showing 6 changed files with 85 additions and 7 deletions.
diff --git a/Makefile b/Makefile
@@ -136,9 +136,11 @@ ZLIB_FLAGS = $(shell pkg-config --cflags zlib)
 ZLIB_LIBS = $(shell pkg-config --libs zlib)
 FYAML_FLAGS = $(shell pkg-config --cflags libfyaml)
 FYAML_LIBS = $(shell pkg-config --libs libfyaml)
+PCRE2_FLAGS = $(shell pkg-config --cflags)
+PCRE2_LIBS = $(shell pkg-config --libs libpcre2-8)
 
-C_FLAGS = -I $(SAIL_LIB_DIR) -I c_emulator $(GMP_FLAGS) $(ZLIB_FLAGS) $(SOFTFLOAT_FLAGS) $(FYAML_FLAGS) -fcommon
-C_LIBS  = $(GMP_LIBS) $(ZLIB_LIBS) $(SOFTFLOAT_LIBS) $(FYAML_LIBS)
+C_FLAGS = -I $(SAIL_LIB_DIR) -I c_emulator $(GMP_FLAGS) $(ZLIB_FLAGS) $(SOFTFLOAT_FLAGS) $(FYAML_FLAGS) $(PCRE2_FLAGS)-fcommon
+C_LIBS  = $(GMP_LIBS) $(ZLIB_LIBS) $(SOFTFLOAT_LIBS) $(FYAML_LIBS) $(PCRE2_LIBS)
 
 # The C simulator can be built to be linked against Spike for tandem-verification.
 # This needs the C bindings to Spike from https://github.com/SRI-CSL/l3riscv

diff --git a/c_emulator/riscv_platform_impl.c b/c_emulator/riscv_platform_impl.c
@@ -3,6 +3,9 @@
 #include <stdio.h>
 
 /* Settings of the platform implementation, with common defaults. */
+char     *RV64ISA                   = "";
+char     *RV32ISA                   = "";
+
 bool rv_enable_pmp                  = false;
 bool rv_enable_zfinx                = false;
 bool rv_enable_rvc                  = true;

diff --git a/c_emulator/riscv_platform_impl.h b/c_emulator/riscv_platform_impl.h
@@ -8,6 +8,9 @@
 // #define DEFAULT_RSTVEC     0x00001000
 #define DEFAULT_RSTVEC     rv_cfg_int_c("/reset/address")
 
+extern char     *RV64ISA;
+extern char     *RV32ISA;
+
 extern bool rv_enable_pmp;
 extern bool rv_enable_zfinx;
 extern bool rv_enable_rvc;

diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c
@@ -13,6 +13,12 @@
 #include <fcntl.h>
 #include <libfyaml.h>
 
+//This macro must be defined before including pcre2.h. For a program that uses
+//only one code unit width, it makes it possible to use generic function names
+//such as pcre2_compile().
+#define PCRE2_CODE_UNIT_WIDTH 8
+#include <pcre2.h>
+
 #include "elf.h"
 #include "sail.h"
 #include "rts.h"
@@ -31,11 +37,12 @@
 struct tv_spike_t;
 #endif
 
-//const char *RV64ISA = "RV64IMAC";
-//const char *RV32ISA = "RV32IMAC";
-
-char *RV64ISA = "";
-char *RV32ISA = "";
+//// TODO:  Move to riscv_platform_impl.c
+////const char *RV64ISA = "RV64IMAC";
+////const char *RV32ISA = "RV32IMAC";
+//
+//char *RV64ISA = "";
+//char *RV32ISA = "";
 
 /* Selected CSRs from riscv-isa-sim/riscv/encoding.h */
 #define CSR_STVEC 0x105
@@ -1018,6 +1025,7 @@ int main(int argc, char **argv)
 {
   // Initialize the RISC-V Configuration elements
   rv_cfg_init();
+//  rv_cfg_configure_c();
 
   // Initialize model so that we can check or report its architecture.
   preinit_sail();

diff --git a/c_emulator/rv_cfg_func.c b/c_emulator/rv_cfg_func.c
@@ -55,8 +55,62 @@ extern char * RV32ISA;      // TODO:  This needs to be in a header file.
 int
 rv_cfg_configure_c()
     {
+    pcre2_code          *re;
+    int                 errornumber;
+    PCRE2_SIZE          erroroffset;
+    pcre2_match_data    *match_data;
+    int                 rc;
+
     RV32ISA = rv_cfg_string_c("/hart0/ISA");
     printf("%s, %d: RV32ISA: '%s'\n", __FILE__, __LINE__, RV32ISA);
+
+    re = pcre2_compile(
+        "C",                    /* the pattern */
+        PCRE2_ZERO_TERMINATED,  /* indicates pattern is zero-terminated */
+        0,                      /* default options */
+        &errornumber,           /* for error number */
+        &erroroffset,           /* for error offset */
+        NULL);                  /* use default compile context */
+
+    if (re == NULL)     // Compilation failed
+        {
+        PCRE2_UCHAR buffer[256];
+        pcre2_get_error_message(errornumber, buffer, sizeof(buffer));
+        printf("PCRE2 compilation failed at offset %d: %s\n", (int)erroroffset,
+                buffer);
+        }    
+
+    match_data = pcre2_match_data_create_from_pattern(re, NULL);
+
+    rc = pcre2_match(
+        re,                   /* the compiled pattern */
+        RV32ISA,              /* the subject string */
+        strlen(RV32ISA),      /* the length of the subject */
+        0,                    /* start at offset 0 in the subject */
+        0,                    /* default options */
+        match_data,           /* block for storing the result */
+        NULL);                /* use default match context */
+
+    printf("%s, %d: rc: %d\n", __FILE__, __LINE__, rc);
+
+    if (rc == 0)
+        {
+        printf("disabling RVC compressed instructions.\n");
+        rv_enable_rvc = false;
+        }
+    else if (rc == 1)
+        {
+        printf("enabling RVC compressed instructions.\n");
+        rv_enable_rvc = true;
+        }
+    else
+        {
+        fprintf(stderr, "%s, %d: unexpected match return value for \"C\" in RV32ISA string: %d\n",
+                __FILE__, __LINE__, rc);
+        exit(1);
+        }
+
+
     }
 
 // ============================================================================

diff --git a/c_emulator/rv_cfg_func.h b/c_emulator/rv_cfg_func.h
@@ -14,6 +14,14 @@
 #include "sail.h" 
 #include <libfyaml.h>
 #include <sys/stat.h>
+#include "riscv_platform_impl.h"
+
+//This macro must be defined before including pcre2.h. For a program that uses
+//only one code unit width, it makes it possible to use generic function names
+//such as pcre2_compile().
+#define PCRE2_CODE_UNIT_WIDTH 8
+#include <pcre2.h>
+
 
 // ==================================================
 // Function prototypes just for the C side of things.