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updated cookbook wrt main loop comment. fixed some compiler warnings
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@billmcspadden-riscv
billmcspadden-riscv committed Aug 8, 2022
1 parent bbf15ae commit c320615
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Showing 12 changed files with 439 additions and 67 deletions.
2 changes: 1 addition & 1 deletion Makefile
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Expand Up @@ -241,7 +241,7 @@ ocaml_emulator/tracecmp: ocaml_emulator/tracecmp.ml

generated_definitions/c/riscv_model_$(ARCH).c: $(SAIL_SRCS) model/main.sail Makefile
mkdir -p generated_definitions/c
$(SAIL) $(SAIL_FLAGS) -O -Oconstant_fold -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h -c_no_main $(SAIL_SRCS) model/main.sail -o $(basename $@)
$(SAIL) $(SAIL_FLAGS) -O -Oconstant_fold -memo_z3 -c -c_include riscv_prelude.h -c_include riscv_platform.h -c_include rv_cfg_func.h -c_no_main $(SAIL_SRCS) model/main.sail -o $(basename $@)

generated_definitions/c2/riscv_model_$(ARCH).c: $(SAIL_SRCS) model/main.sail Makefile
mkdir -p generated_definitions/c2
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1 change: 1 addition & 0 deletions c_emulator/riscv_platform_impl.c
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Expand Up @@ -5,6 +5,7 @@
/* Settings of the platform implementation, with common defaults. */
char *RV64ISA = "";
char *RV32ISA = "";
char *RV128ISA = "";

bool rv_enable_pmp = false;
bool rv_enable_zfinx = false;
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1 change: 1 addition & 0 deletions c_emulator/riscv_platform_impl.h
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Expand Up @@ -10,6 +10,7 @@

extern char *RV64ISA;
extern char *RV32ISA;
extern char *RV128ISA;

extern bool rv_enable_pmp;
extern bool rv_enable_zfinx;
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77 changes: 31 additions & 46 deletions c_emulator/riscv_sim.c
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Expand Up @@ -37,13 +37,6 @@
struct tv_spike_t;
#endif

//// TODO: Move to riscv_platform_impl.c
////const char *RV64ISA = "RV64IMAC";
////const char *RV32ISA = "RV32IMAC";
//
//char *RV64ISA = "";
//char *RV32ISA = "";

/* Selected CSRs from riscv-isa-sim/riscv/encoding.h */
#define CSR_STVEC 0x105
#define CSR_SEPC 0x141
Expand Down Expand Up @@ -90,16 +83,6 @@ bool config_print_mem_access = true;
bool config_print_platform = true;
bool config_print_rvfi = false;

///* RISC-V Config YAML configuration support */
//char *rv_config_platform_file = NULL;
//int rv_config_platform_fd = 0;
//struct fy_document *rv_config_fyd_platform = NULL;
//
//char *rv_config_isa_file = NULL;
//int rv_config_isa_fd = 0;
//struct fy_document *rv_config_fyd_isa = NULL;


void set_config_print(char *var, bool val) {
if (var == NULL || strcmp("all", var) == 0) {
config_print_instr = val;
Expand Down Expand Up @@ -132,13 +115,13 @@ char *sailcov_file = NULL;

static struct option options[] = {
{"enable-dirty-update", no_argument, 0, 'd'},
{"enable-misaligned", no_argument, 0, 'm'},
// {"enable-misaligned", no_argument, 0, 'm'},
{"enable-pmp", no_argument, 0, 'P'},
{"enable-next", no_argument, 0, 'N'},
// {"enable-next", no_argument, 0, 'N'},
{"ram-size", required_argument, 0, 'z'},
{"disable-compressed", no_argument, 0, 'C'},
// {"disable-compressed", no_argument, 0, 'C'},
{"disable-writable-misa", no_argument, 0, 'I'},
{"disable-fdext", no_argument, 0, 'F'},
// {"disable-fdext", no_argument, 0, 'F'},
{"mtval-has-illegal-inst-bits", no_argument, 0, 'i'},
{"device-tree-blob", required_argument, 0, 'b'},
{"terminal-log", required_argument, 0, 't'},
Expand All @@ -153,7 +136,7 @@ static struct option options[] = {
{"trace", optional_argument, 0, 'v'},
{"no-trace", optional_argument, 0, 'V'},
{"inst-limit", required_argument, 0, 'l'},
{"enable-zfinx", no_argument, 0, 'x'},
// {"enable-zfinx", no_argument, 0, 'x'},
{"platform-config", required_argument, 0, 'y'},
{"isa-config", required_argument, 0, 'u'},
#ifdef SAILCOV
Expand Down Expand Up @@ -245,12 +228,12 @@ char *process_args(int argc, char **argv)
c = getopt_long(argc, argv,
"a"
"d"
"m"
// "m"
"P"
// "C"
"N"
// "N"
"I"
"F"
// "F"
"i"
"s"
"p"
Expand All @@ -268,7 +251,7 @@ char *process_args(int argc, char **argv)
"V::"
"v::"
"l:"
"x"
// "x"
#ifdef SAILCOV
"c:"
#endif
Expand All @@ -295,10 +278,10 @@ char *process_args(int argc, char **argv)
fprintf(stderr, "enabling dirty update.\n");
rv_enable_dirty_update = true;
break;
case 'm':
fprintf(stderr, "enabling misaligned access.\n");
rv_enable_misaligned = true;
break;
// case 'm':
// fprintf(stderr, "enabling misaligned access.\n");
// rv_enable_misaligned = true;
// break;
case 'P':
fprintf(stderr, "enabling PMP support.\n");
rv_enable_pmp = true;
Expand All @@ -307,18 +290,18 @@ char *process_args(int argc, char **argv)
// fprintf(stderr, "disabling RVC compressed instructions.\n");
// rv_enable_rvc = false;
// break;
case 'N':
fprintf(stderr, "enabling N extension.\n");
rv_enable_next = true;
break;
// case 'N':
// fprintf(stderr, "enabling N extension.\n");
// rv_enable_next = true;
// break;
case 'I':
fprintf(stderr, "disabling writable misa CSR.\n");
rv_enable_writable_misa = false;
break;
case 'F':
fprintf(stderr, "disabling floating point (F and D extensions).\n");
rv_enable_fdext = false;
break;
// case 'F':
// fprintf(stderr, "disabling floating point (F and D extensions).\n");
// rv_enable_fdext = false;
// break;
case 'i':
fprintf(stderr, "enabling storing illegal instruction bits in mtval.\n");
rv_mtval_has_illegal_inst_bits = true;
Expand Down Expand Up @@ -375,11 +358,11 @@ char *process_args(int argc, char **argv)
case 'l':
insn_limit = atoi(optarg);
break;
case 'x':
fprintf(stderr, "enabling Zfinx support.\n");
rv_enable_zfinx = true;
rv_enable_fdext = false;
break;
// case 'x':
// fprintf(stderr, "enabling Zfinx support.\n");
// rv_enable_zfinx = true;
// rv_enable_fdext = false;
// break;
#ifdef SAILCOV
case 'c':
sailcov_file = strdup(optarg);
Expand Down Expand Up @@ -1023,10 +1006,12 @@ void init_logs()

int main(int argc, char **argv)
{
char *file = process_args(argc, argv);
// Initialize the RISC-V Configuration elements
rv_cfg_init();
// rv_cfg_configure_c();
char *file = process_args(argc, argv);
// Initialize the RISC-V Configuration elements.
// Must be done after command line arguments are processed in
// order to get RISCV-Config filenames.
rv_cfg_configure_c();

// Initialize model so that we can check or report its architecture.
preinit_sail();
Expand Down
123 changes: 107 additions & 16 deletions c_emulator/rv_cfg_func.c
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Original file line number Diff line number Diff line change
Expand Up @@ -36,6 +36,8 @@ static rv_cfg_enum2string_t rv_cfg_enum2string_init_a[] =

static rv_cfg_enum2doc_t rv_cfg_enum2doc_a[RV_CFG_LAST];

extern int64_t zxlen_val;

// ============================================================================
int
rv_cfg_init()
Expand All @@ -49,23 +51,113 @@ rv_cfg_init()
}

// ============================================================================
int
rv_cfg_configure_c()
{
char * RV_ISA;

RV_ISA = rv_cfg_string_c("/hart0/ISA");
printf("%s, %d: RV_ISA: '%s'\n", __FILE__, __LINE__, RV_ISA);

rv_enable_rvc = rv_cfg_ext_enable_c(RV_ISA, "C");
rv_enable_fdext = rv_cfg_ext_enable_c(RV_ISA, "F");
rv_enable_next = rv_cfg_ext_enable_c(RV_ISA, "N");
rv_enable_zfinx = rv_cfg_ext_enable_c(RV_ISA, "Zfinx");

rv_enable_misaligned = rv_cfg_bool_c("/hart0/hw_data_misaligned_support");



// // ====================================
// // Error checking of configuration. XLEN
// printf("%s, %d: zxlen_val: %ld\n", __FILE__, __LINE__, zxlen_val);
// if (zxlen_val == 32)
// {
// if (!rv_cfg_ext_enable_c(RV_ISA, "RV32"))
// {
// fprintf(stderr, "%s, %d: incompatable settings for zxlen_val and RV_ISA. both must be 32.",
// __FILE__, __LINE__);
// exit(1);
// }
// RV32ISA = RV_ISA;
// }
// else if (zxlen_val == 64)
// {
// if (!rv_cfg_ext_enable_c(RV_ISA, "RV64"))
// {
// fprintf(stderr, "%s, %d: incompatable settings for zxlen_val and RV_ISA. both must be 64.",
// __FILE__, __LINE__);
// exit(1);
// }
// RV64ISA = RV_ISA;
// }
// else if (zxlen_val == 128)
// {
// if (!rv_cfg_ext_enable_c(RV_ISA, "RV128"))
// {
// fprintf(stderr, "%s, %d: incompatable settings for zxlen_val and RV_ISA. both must be 128.",
// __FILE__, __LINE__);
// exit(1);
// }
// RV128ISA = RV_ISA;
// }
// else
// {
// fprintf(stderr, "%s, %d: invalid setting for zxlen_val: %d.",
// __FILE__, __LINE__, zxlen_val);
// }

// ====================================
// Check extension settings
if ((rv_enable_fdext == true) && (rv_enable_zfinx == true))
{
fprintf(stderr, "%s, %d: incompatable settings for [fd]ext and Zfinx. both cannot be enabled.",
__FILE__, __LINE__);
exit(1);
}

// ====================================
// Print out the configuration settings


}

// ============================================================================
bool
rv_cfg_bool_c(char * key_str)
{
char *s;

extern char * RV32ISA; // TODO: This needs to be in a header file.
s = rv_cfg_string_c(key_str);

if ( strcmp("true", s) == 0)
{
return(true);
}
else if ( strcmp("false", s) == 0 )
{
return(false);
}
else
{
fprintf(stderr, "%s, %d: internal error. '%s' does not appear to be a bool.\n",
__FILE__, __LINE__, key_str);
exit(1);
}
}

// ============================================================================
int
rv_cfg_configure_c()
rv_cfg_ext_enable_c(char * isa_str, char * ext_pattern)
{
pcre2_code *re;
int errornumber;
PCRE2_SIZE erroroffset;
pcre2_match_data *match_data;
int rc;

RV32ISA = rv_cfg_string_c("/hart0/ISA");
printf("%s, %d: RV32ISA: '%s'\n", __FILE__, __LINE__, RV32ISA);

re = pcre2_compile(
"C", /* the pattern */
ext_pattern, /* the pattern */
PCRE2_ZERO_TERMINATED, /* indicates pattern is zero-terminated */
0, /* default options */
&errornumber, /* for error number */
Expand All @@ -84,29 +176,27 @@ rv_cfg_configure_c()

rc = pcre2_match(
re, /* the compiled pattern */
RV32ISA, /* the subject string */
strlen(RV32ISA), /* the length of the subject */
isa_str, /* the subject string */
strlen(isa_str), /* the length of the subject */
0, /* start at offset 0 in the subject */
0, /* default options */
match_data, /* block for storing the result */
NULL); /* use default match context */

printf("%s, %d: rc: %d\n", __FILE__, __LINE__, rc);

if (rc == 0)
if ((rc == 0) || (rc == -1))
{
printf("disabling RVC compressed instructions.\n");
rv_enable_rvc = false;
return(0);
}
else if (rc == 1)
{
printf("enabling RVC compressed instructions.\n");
rv_enable_rvc = true;
return(1);
}
else
{
fprintf(stderr, "%s, %d: unexpected match return value for \"C\" in RV32ISA string: %d\n",
__FILE__, __LINE__, rc);
fprintf(stderr, "%s, %d: unexpected match return value, %d, for '%s' in ISA string %s\n",
__FILE__, __LINE__, rc, ext_pattern, isa_str);
exit(1);
}

Expand Down Expand Up @@ -286,7 +376,8 @@ rv_cfg_int(sail_int *zret_int, char * yaml_key_str)

// ============================================================================
int
rv_cfg_string(sail_string **s, char * yaml_key_str)
//rv_cfg_string(sail_string **s, char * yaml_key_str)
rv_cfg_string(sail_string s, char * yaml_key_str)
{
printf("%s, %d: entering rv_cfg_string()\n", __FILE__, __LINE__);
s = rv_cfg_string_c(yaml_key_str);
Expand Down
6 changes: 4 additions & 2 deletions c_emulator/rv_cfg_func.h
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Original file line number Diff line number Diff line change
Expand Up @@ -60,6 +60,8 @@ char * rv_cfg_string_c(char *);
bool rv_cfg_bool_c(char *);
int rv_cfg_configure_c(void);
void rv_cfg_dump_yaml_c(char *);
int rv_cfg_ext_enable_c(char * isa_str, char * ext_pattern);
bool rv_cfg_bool_c(char * key_str);



Expand All @@ -76,8 +78,8 @@ void rv_cfg_dump_yaml_c(char *);
//INT_RET_TYPE rv_cfg_int(sail_int *, char *, unit); // TODO: find out why unit is sometimes required, sometimes not INT_RET_TYPE rv_cfg_int(sail_int *, char *);

int rv_cfg_int(sail_int *, char *);
int rv_cfg_string(sail_string **, char *);
int rv_cfg_bool(sail_string *, char *);
int rv_cfg_string(sail_string , char *);
int rv_cfg_bool(sail_string , char *);
unit rv_cfg_dump_yaml(char *);

//#endif
8 changes: 7 additions & 1 deletion cookbook/doc/RISCV_model_FAQ.adoc
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Original file line number Diff line number Diff line change
Expand Up @@ -56,7 +56,13 @@ the RISCV_config YAML structure, the MTIMER can be assigned any address.
[#q__is_the__main_loop__coded_in_Sail]
==== Q: Is the "main loop" coded in Sail?
A: Yes. The main execution loop can be found in main.sail.
A: The initial answer to this question ("The main execution loop can be found in `main.sail``.")
is incorrect. main.sail is not executed in the RISC-V model, even though it is
compiled into the model.
The main loop is actually found on the C side in the file `c_emulator/riscv_sim.c`
in the function `run_sail()``. In this function, the Sail function, `zstep()`, is
called (which is the Sail function, `step()` )
[#q-can-gdb-attach-to-the-riscv-golden-model-to-debug-riscv-code]
==== Q: Can gdb attach to the RISCV Golden Model to debug RISCV code?
Expand Down
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