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non-functional changes only. renamed functions to rv_cfg_c (for C rou…
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…tines) and rv_cfg_s (for Sail routines). removed commented-out code.
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@billmcspadden-riscv
billmcspadden-riscv committed Aug 15, 2022
1 parent d1afe6d commit 260e497
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Showing 7 changed files with 64 additions and 142 deletions.
2 changes: 1 addition & 1 deletion c_emulator/riscv_platform_impl.h
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
/* Settings of the platform implementation. */

// #define DEFAULT_RSTVEC 0x00001000
#define DEFAULT_RSTVEC rv_cfg_int_c("/reset/address")
#define DEFAULT_RSTVEC rv_cfg_c_int("/reset/address")

extern char *RV64ISA;
extern char *RV32ISA;
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73 changes: 4 additions & 69 deletions c_emulator/riscv_sim.c
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Original file line number Diff line number Diff line change
Expand Up @@ -114,14 +114,6 @@ char *sailcov_file = NULL;
#endif

static struct option options[] = {
// {"enable-dirty-update", no_argument, 0, 'd'},
// {"enable-misaligned", no_argument, 0, 'm'},
// {"enable-pmp", no_argument, 0, 'P'},
// {"enable-next", no_argument, 0, 'N'},
// {"ram-size", required_argument, 0, 'z'},
// {"disable-compressed", no_argument, 0, 'C'},
// {"disable-writable-misa", no_argument, 0, 'I'},
// {"disable-fdext", no_argument, 0, 'F'},
{"mtval-has-illegal-inst-bits", no_argument, 0, 'i'},
{"device-tree-blob", required_argument, 0, 'b'},
{"terminal-log", required_argument, 0, 't'},
Expand All @@ -136,7 +128,6 @@ static struct option options[] = {
{"trace", optional_argument, 0, 'v'},
{"no-trace", optional_argument, 0, 'V'},
{"inst-limit", required_argument, 0, 'l'},
// {"enable-zfinx", no_argument, 0, 'x'},
{"platform-config", required_argument, 0, 'y'},
{"isa-config", required_argument, 0, 'u'},
#ifdef SAILCOV
Expand Down Expand Up @@ -227,17 +218,10 @@ char *process_args(int argc, char **argv)
while(true) {
c = getopt_long(argc, argv,
"a"
// "d"
// "m"
// "P"
// "C"
// "N"
"I"
// "F"
"i"
"s"
"p"
// "z:"
"b:"
"t:"
"T:"
Expand All @@ -251,57 +235,28 @@ char *process_args(int argc, char **argv)
"V::"
"v::"
"l:"
// "x"
#ifdef SAILCOV
"c:"
#endif
, options, NULL);
if (c == -1) break;
switch (c) {
case 'y':
if ( rv_cfg_build_from_file(RV_CFG_PLATFORM, optarg) == 0 ) {
if ( rv_cfg_c_build_from_file(RV_CFG_PLATFORM, optarg) == 0 ) {
fprintf(stderr, "unable to build fast-yaml document from %s\n", optarg);
exit(1);
}
break;

case 'u':
if ( rv_cfg_build_from_file(RV_CFG_ISA, optarg) == 0 ) {
if ( rv_cfg_c_build_from_file(RV_CFG_ISA, optarg) == 0 ) {
fprintf(stderr, "unable to build fast-yaml document from %s\n", optarg);
exit(1);
}
break;
case 'a':
report_arch();
break;
// case 'd':
// fprintf(stderr, "enabling dirty update.\n");
// rv_enable_dirty_update = true;
// break;
// case 'm':
// fprintf(stderr, "enabling misaligned access.\n");
// rv_enable_misaligned = true;
// break;
// case 'P':
// fprintf(stderr, "enabling PMP support.\n");
// rv_enable_pmp = true;
// break;
// case 'C':
// fprintf(stderr, "disabling RVC compressed instructions.\n");
// rv_enable_rvc = false;
// break;
// case 'N':
// fprintf(stderr, "enabling N extension.\n");
// rv_enable_next = true;
// break;
// case 'I':
// fprintf(stderr, "disabling writable misa CSR.\n");
// rv_enable_writable_misa = false;
// break;
// case 'F':
// fprintf(stderr, "disabling floating point (F and D extensions).\n");
// rv_enable_fdext = false;
// break;
case 'i':
fprintf(stderr, "enabling storing illegal instruction bits in mtval.\n");
rv_mtval_has_illegal_inst_bits = true;
Expand All @@ -313,16 +268,6 @@ char *process_args(int argc, char **argv)
fprintf(stderr, "will show execution times on completion.\n");
do_show_times = true;
break;
// case 'z':
// ram_size = atol(optarg);
// if (ram_size) {
// fprintf(stderr, "setting ram-size to %" PRIu64 " MB\n", ram_size);
// rv_ram_size = ram_size << 20;
// } else {
// fprintf(stderr, "invalid ram-size '%s' provided.\n", optarg);
// exit(1);
// }
// break;
case 'b':
dtb_file = strdup(optarg);
fprintf(stderr, "using %s as DTB file.\n", dtb_file);
Expand Down Expand Up @@ -358,11 +303,6 @@ char *process_args(int argc, char **argv)
case 'l':
insn_limit = atoi(optarg);
break;
// case 'x':
// fprintf(stderr, "enabling Zfinx support.\n");
// rv_enable_zfinx = true;
// rv_enable_fdext = false;
// break;
#ifdef SAILCOV
case 'c':
sailcov_file = strdup(optarg);
Expand Down Expand Up @@ -555,10 +495,7 @@ void init_sail_reset_vector(uint64_t entry)
/* set rom size */
rv_rom_size = rom_end - rv_rom_base;
/* boot at reset vector */
// zPC = rv_rom_base;
// zPC = rv_cfg_int_c("/reset/address");
zPC = rv_reset_address;
// printf("%s, %d: reset address: 0x%lx\n", __FILE__, __LINE__, zPC);
}

void preinit_sail()
Expand Down Expand Up @@ -1007,19 +944,17 @@ void init_logs()

int main(int argc, char **argv)
{
rv_cfg_init();
rv_cfg_c_init();
char *file = process_args(argc, argv);
// Initialize the RISC-V Configuration elements.
// Must be done after command line arguments are processed in
// order to get RISCV-Config filenames.
rv_cfg_configure_c();
rv_cfg_c_configure();

// Initialize model so that we can check or report its architecture.
preinit_sail();

// char *file = process_args(argc, argv);
init_logs();
// rv_cfg_configure_c();

if (gettimeofday(&init_start, NULL) < 0) {
fprintf(stderr, "Cannot gettimeofday: %s\n", strerror(errno));
Expand Down
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