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Issues: riscv/riscv-p-spec
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SIMD instruction for loading values into the register at same time.
#38
opened Feb 24, 2021 by
subhajit26
CLZ32 overlap with CLZ[W] in Zbb
Overlap with existing extension
#53
opened May 25, 2021 by
aswaterman
MINW/MAXW overlap with MIN/MAX in Zbb
Overlap with existing extension
#54
opened May 25, 2021 by
aswaterman
BPICK overlap with CMIX in Zbt
Overlap with existing extension
#55
opened May 25, 2021 by
aswaterman
WEXT[I] overlap with FSR[I][W] in Zbt
Overlap with existing extension
#57
opened May 25, 2021 by
aswaterman
SWAP8 overlap with REV8.H (GREVI) in Zbp
Overlap with existing extension
#58
opened May 25, 2021 by
aswaterman
BITREV[I] partially overlaps REV (GREVI) in Zbp
Overlap with existing extension
#59
opened May 25, 2021 by
aswaterman
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