This release was created by: kdockser
Release of RISC-V ISA, built from commit e7cb4f3, is now available.
What's Changed
- [vector crypto] Clarifying mandate for vector register index alignment to LMUL/EMUL by @nibrunieAtSi5 in #1653
Full Changelog: riscv-isa-release-bd45a11-2024-11-26...riscv-isa-release-e7cb4f3-2024-11-26