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Add support for the Zicond ISA extension
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The upcoming Zicond ISA extension introduces two new instructions:
* czero.eqz
* czero.nez

This patch adds these instructions to template.yaml.

The Zicond ISA extension is documented here:
  https://github.com/riscv/riscv-zicond/blob/main/zicondops.adoc

Signed-off-by: Christoph Müllner <[email protected]>
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cmuellner committed Mar 21, 2023
1 parent 9d3cd14 commit 1e62d08
Showing 1 changed file with 42 additions and 0 deletions.
42 changes: 42 additions & 0 deletions riscv_ctg/data/template.yaml
Original file line number Diff line number Diff line change
@@ -10299,3 +10299,45 @@ unshfli:
unshfli $rd, $rs1, $imm_val
SREG $rd, $offset($swreg)
RVMODEL_IO_ASSERT_GPR_EQ($testreg, $rd, $correctval)
czero.eqz:
std_op:
sig:
stride: 1
sz: 'XLEN/8'
xlen: [32,64]
isa:
- IZicond
operation: 'hex(int(rs2_val != 0) * rs1_val)'
formattype: 'rformat'
rs1_op_data: *all_regs
rs2_op_data: *all_regs
rd_op_data: *all_regs
rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
template: |-
// $comment
// opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val
TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)
czero.nez:
std_op:
sig:
stride: 1
sz: 'XLEN/8'
xlen: [32,64]
isa:
- IZicond
operation: 'hex(int(rs2_val == 0) * rs1_val)'
formattype: 'rformat'
rs1_op_data: *all_regs
rs2_op_data: *all_regs
rd_op_data: *all_regs
rs1_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
rs2_val_data: 'gen_sign_dataset(xlen) + gen_sp_dataset(xlen,True)'
template: |-
// $comment
// opcode: $inst ; op1:$rs1; op2:$rs2; dest:$rd; op1val:$rs1_val; op2val:$rs2_val
TEST_RR_OP($inst, $rd, $rs1, $rs2, $correctval, $rs1_val, $rs2_val, $swreg, $offset, $testreg)

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