Update reference algorithm to cover missing trap handling case - Issu…

…e 187

exampleAlgorithm.adoc

@@ -9,7 +9,7 @@ A reference algorithm for compressed branch trace is given in
 * _te_inst._ The name of the packet type emitted by the encoder (see
 <<packets>>);
 * _inst._ Abbreviation for 'instruction';
-* _exception. Exception or interrupt signalled;_
+* _trap. Exception or interrupt signalled;_
 * _updiscon._ Uninferable PC discontinuity. This identifies an
 instruction that causes the program counter to be changed by an amount
 that cannot be predicted from the source code alone (*itype* values 8,
@@ -24,21 +24,15 @@ not;
 reported precisely or treated as an uninferable PC discontinuity (see
 <<tab:context-type>>);
 * _ppccd_br._ As above, but branch map not empty;
-* _er_n._ Instruction retirement and exception signalled on the same
-cycle, or Trace notify trigger (see
-<<tab:debugModuleTriggerSupport>>);
-* _exc_only._ Exception or interrupt signalled without simultaneous
-retirement;
+* _ntf._ Trace notify trigger (see <<tab:debugModuleTriggerSupport>>);
 * _cci._ context change that can be reported imprecisely (see
 <<tab:context-type>>);
 * _rpt_br._ Report branches due to full branch map or misprediction;
 * _branches._ The number of branches encountered but not yet reported to
 the decoder;
 * _pbc._ Correctly predicted branches count (always zero if branch
 predictor disabled or not present);
-* _Reported?_ "Exception previous" reported with *thaddr* = 0 on the
-cycle it occured because it was preceded by an updiscon or immediately
-followed by another exception;
+* _trep_ Previous trap already reported with *thaddr* = 0 because it was preceded by an updiscon or immediately followed by another exception;
 * _resync count._ A counter used to keep track of when it is necessary
 to send a synchronization packet (see <<sec:resync>>);
 * _max_resync._ The resync counter value that schedules a
@@ -52,7 +46,7 @@ would be seen in a single-retirement system only. Whilst the core to
 encoder interface allows the RISC-V hart to provide information on
 multiple retiring instructions simultaneously, the resultant packet
 sequence generated by the encoder must be the same as if retiring one
-instruction at a time.
+instruction at a time.  Note that even with a single-retirement system it is possible to retire an instruction and report a trap simultaneously (*itype* = 1 or 2 and *iretire* = 1).  In this case the flow diagram must be traversed twice, first for the retired instruction, and then for the trap.
 
 A 3-stage pipeline within the encoder is assumed, such that the encoder
 has visibility of the current, previous and next instructions. All