PMM ACTs

coverage/header_file.yaml

@@ -67,6 +67,7 @@ common:
  SATP64_ASID: 0x0FFFF00000000000
  SATP64_PPN: 0x00000FFFFFFFFFFF
  SATP_MODE_OFF: 0
+
  SATP_MODE_SV32: 1
  SATP_MODE_SV39: 8
  SATP_MODE_SV48: 9
@@ -922,6 +923,13 @@ PMP_MACROS:
  PMPCFG_RW_BIT: 0x60
  PMPCFG_L_BIT: 0x80
  PMPCFG_ALL_BIT: 0xFF
+
+PMM_MACROS:
+ PMM_MASK: 0x300000000
+ PMM_MASK_SV57: 0x200000000
+ PMM_MASK_SV48: 0x300000000
+ PMM_MASK_DISABLED: 0x000000000
+
 
 PMP_helper_Coverpoints:
  NAPOT_REGION_ADDRESS_MATCH:  ((rs1_val + imm_val) ^ (pmpaddr1<<2)) &  ~(((pmpaddr1 ^ (pmpaddr1+1))<<2) | 3) ==0 and ((rs1_val+imm_val+access_len-1 ) ^ (pmpaddr1<<2)) &  ~(((pmpaddr1 ^ (pmpaddr1+1))<<2) | 3) ==0
@@ -932,4 +940,4 @@ PMP_helper_Coverpoints:
  TOR_PRIORITY_2_REGION_MATCH: (rs1_val + imm_val >= (pmpaddr0 << 2)) and (rs1_val + imm_val < (pmpaddr1 << 2))
  NA4_REGION_ADDRESS_MATCH: (rs1_val + imm_val == (pmpaddr1 << 2))
  NA4_PRIORITY_REGION_MATCH: (rs1_val + imm_val == (pmpaddr3 << 2))
- NA4_PRIORITY_2_REGION_MATCH: (rs1_val + imm_val == (pmpaddr1 << 2))
+ NA4_PRIORITY_2_REGION_MATCH: (rs1_val + imm_val == (pmpaddr1 << 2))

riscv-test-suite/env/arch_test.h

@@ -1418,7 +1418,7 @@ adj_\__MODE__\()epc_rtn:                // adj mepc so there is at least 4B of p
 
 /**** FIXME: if in Mmode and mode!=bare & MPRV=1, then T4 be altered to point to
              the mode of the mstatus.mpp that is stored in Xtrampend_sv ****/
-
+#ifndef PMM_EXT_ENAB
         csrr    T2, CSR_XTVAL
 
 chk_\__MODE__\()tval:
@@ -1461,7 +1461,7 @@ adj_\__MODE__\()tval:
 
 sv_\__MODE__\()tval:
         SREG    T3, 3*REGWIDTH(T1)      // save 4th sig value, (rel tval)
-
+#endif
 skp_\__MODE__\()tval:
 
   .ifc \__MODE__ , M

riscv-test-suite/env/test_macros.h

@@ -30,6 +30,16 @@
 #define SIG  sig_bgn_off
 #define VMEM vmem_bgn_off
 
+//This macro is used to go from M -> M with virtualization enabled
+#define ENABLE_VIRT_MMODE()      ;\
+	LI (s7, MSTATUS_MPRV)           ;\
+	csrs mstatus,s7                 ;\
+	LI (s7, MSTATUS_MPP)            ;\
+	csrs mstatus,s7                 ;\
+	auipc t0, 0					    ;\
+	addi t0, t0, 16					;\
+	csrw mepc, t0					;\
+	mret;
 
 #define SATP_SETUP(_TR0, _TR1, MODE);\
     LA(_TR0, rvtest_Sroot_pg_tbl) ;\

riscv-test-suite/rv64i_m/pmm/pmm_atomics/PMM_atomic_01_M_sv48_tag00.S

@@ -0,0 +1,237 @@
+/* 
+Verification Goal: Set PMM = 00 in the msecccfg and tag bits are 0x0000 with bit[47]=0,
+test whether or not pointer masking with PMLEN = 16 is enabled or not in M-Mode in sv48
+Description:       
+If Pointer Masking is enabled, then the Effective Address will be masked accordingly, no exception will be generated,
+If Pointer Masking is disabled, then the Effective Address will be valid, no exception will be created
+due to the invalid Virtual Address,
+*/
+
+#define PMM_EXT_ENAB
+#include "model_test.h"
+#include "arch_test.h"
+
+RVTEST_ISA("RV64IA_Zicsr")
+
+# Test code region
+.section .text.init
+.globl rvtest_entry_point
+rvtest_entry_point:
+RVMODEL_BOOT
+RVTEST_CODE_BEGIN
+#ifdef TEST_CASE_1
+
+    RVTEST_CASE(1,"//check ISA:=regex(.*64.*); check ISA:=regex(.*I.*A.*Zicsr.*); def rvtest_mtrap_routine=True; def rvtest_strap_routine=True; def TEST_CASE_1=True; mac PMM_MACROS",pm_atomic_M_mode_SV48_tag00)
+
+RVTEST_SIGBASE( x13,signature_x13_1)
+
+
+main:
+# ------------------------ Set the PMP for all memory regions -----------------
+	ALL_MEM_PMP
+# ------------------------------------------------------------------------------
+
+	csrw satp, zero								// Set satp to zero (bare mode)
+
+# --------------------------- Define Addresses -------------------------------
+	.set pa_rvtest_code_begin,  	0x8000000000039c      // 56-bit physical address of the code section
+	.set pa_rvtest_data_begin,  	0x80000000003530      // 56-bit physical address of the data section
+	.set pa_rvtest_sig_begin, 		0x80000000006218      // 56-bit physical address of the signature section
+	.set va_rvtest_code_begin,  	0x008000000000039c    // 48-bit virtual address of the code section						
+	.set va_rvtest_data_begin,  	0x0000500000000000    // 48-bit virtual address of the data section
+	.set va_rvtest_sig_begin,   	0x0000500000006218    // 48-bit virtual address of the signature section
+	.set  va_rvtest_vmem_begin, 	0x0000500000000000    // 48-bit virtual address of vmem
+
+# ------------------------------------------------------------------------------
+
+# ------------------------ Save Area Logic ------------------------------------
+
+	/* Save virtual addresses of code and data in the S-mode save area */
+
+	LI (t0, va_rvtest_data_begin)          // Load virtual address of data
+	LA (t1, rvtest_data_begin)             // Load physical address of data
+	sub t0, t0, t1                         // Calculate (VA - PA)
+	addi t3, t0, sv_area_sz                // Adjust for save area size
+	csrr sp, mscratch                      // Read from mscratch
+	add t1, sp, t3                         // Add save area offset to stack pointer
+	csrw sscratch, t1                      // Write new value to sscratch
+
+	LI (t0, va_rvtest_code_begin)          // Load virtual address of code
+	LA (t1, rvtest_code_begin)             // Load physical address of code
+    sub t0, t0, t1                         // Calculate (VA - PA)
+	csrr sp, mscratch                      // Read from mscratch
+	LREG t1, code_bgn_off+0*sv_area_sz(sp) // Load base address of code save area
+	add t2, t1, t0                         // Add offset for code
+	SREG t2, code_bgn_off+1*sv_area_sz(sp) // Save adjusted code address
+
+	LI (t0, va_rvtest_data_begin)          // Load virtual address of data
+	LA (t1, rvtest_data_begin)             // Load physical address of data
+	sub t0, t0, t1                         // Calculate (VA - PA)
+	LREG t1, data_bgn_off+0*sv_area_sz(sp) // Load base address of data save area
+	add t2, t1, t0                         // Add offset for data
+	SREG t2, data_bgn_off+1*sv_area_sz(sp) // Save adjusted data address
+
+	LI (t0, va_rvtest_sig_begin)           // Load virtual address of signature
+	LA (t1, rvtest_sig_begin)              // Load physical address of signature
+	sub t0, t0, t1                         // Calculate (VA - PA)
+	LREG t1, sig_bgn_off+0*sv_area_sz(sp)  // Load base address of signature save area
+	add t2, t1, t0                         // Add offset for signature
+	SREG t2, sig_bgn_off+1*sv_area_sz(sp)  // Save adjusted signature address
+
+	// vmem
+	LI (t0, va_rvtest_vmem_begin)          // Load virtual address of vmem
+	LA (t1, rvtest_data_begin)             // Load physical address of data
+	sub t0, t0, t1                         // Calculate (VA - PA)
+	LREG t1, vmem_bgn_off+0*sv_area_sz(sp) // Load base address of vmem save area
+	add t2, t1, t0                         // Add offset for vmem
+	SREG t2, vmem_bgn_off+1*sv_area_sz(sp) // Save adjusted vmem address
+
+# --------------------- Set the Level 3 PTE for SV48 -------------------------
+
+	// Set level 3 PTE for the code area (PA: 0x200000000000 -> VA: 0x80000000000000)
+	LI (a0, pa_rvtest_code_begin)          // Load physical address of code
+	LI (a1, (PTE_V | PTE_A | PTE_W | PTE_R | PTE_D | PTE_X| PTE_U)) // Set permission bits
+	PTE_SETUP_RV64(a0, a1, t0, t1, va_rvtest_code_begin, LEVEL3, sv48) // Set up level 3 PTE
+
+	// Set level 3 PTE for the data area
+	LI (a0, pa_rvtest_code_begin)
+	LI (a1, (PTE_V | PTE_A | PTE_W | PTE_R | PTE_D | PTE_X| PTE_U))
+	PTE_SETUP_RV64(a0, a1, t0, t1, va_rvtest_data_begin, LEVEL3, sv48)
+
+# --------------------- Set the Level 3 PTE for Signature ---------------------
+	// Set level 3 PTE for the signature area
+	LI (a0, pa_rvtest_code_begin)          // Load physical address of signature area
+	LI (a1, (PTE_V | PTE_A | PTE_W | PTE_R | PTE_D | PTE_X| PTE_U)) // Set permission bits
+	PTE_SETUP_RV64(a0, a1, t0, t1, va_rvtest_sig_begin, LEVEL3, sv48) // PTE setup
+
+	LI (t0, va_rvtest_sig_begin)           // Load virtual address of signature
+	LI (t1, pa_rvtest_sig_begin)           // Load physical address of signature
+	sub t0, t0, t1                         // Calculate (VA - PA)
+	add x13, x13, t0                       // Adjust signature register
+
+# -------------------- Set SATP for Virtualization ----------------------------
+
+	sfence.vma                             // Flush the TLB
+satp_setup:
+	SATP_SETUP_RV64(sv48)                  // Set SATP for SV48 mode
+
+# -------------------- Enter and Exit M Mode ----------------------------------
+
+	ENABLE_VIRT_MMODE()
+
+# -------------------- Test PMM (Pointer Masking) without Masking --------------
+
+vm_en:
+	nop
+	LI (x8, va_rvtest_data_begin)          // Load virtual address of data
+	nop
+	sfence.vma
+	lr.w a2, 0(x8)                         // Test load access
+	nop
+	sfence.vma
+	sc.w t1, a2, 0(x8)                     // Test store access
+	nop
+	sfence.vma
+	lr.d a2, 0(x8)                         // Test load access
+	nop
+	sfence.vma
+	sc.d t1, a2, 0(x8)                     // Test store access
+	nop
+
+# -------------------- Disable Virtualization ---------------------------------
+
+	RVTEST_GOTO_MMODE                     // Switch back to Machine mode
+
+# -------------------- Enable Pointer Masking (PMM) ---------------------------
+
+	LI a3, 0x300000000
+	csrw mseccfg, a3                      // Enable pointer masking with PMLEN = 16
+
+# -------------------- Set SATP for Virtualization ----------------------------
+
+
+	ENABLE_VIRT_MMODE()
+	csrr t0, satp
+# -------------------- Test PMM with Masking Enabled --------------------------
+
+vm_en_with_pointer_masking:
+	LI (x8, va_rvtest_data_begin)          // Load virtual address of data
+	nop
+	sfence.vma
+	lr.w a2, 0(x8)                         // Test load access
+	nop
+	sfence.vma
+	sc.w t1, a2, 0(x8)                     // Test store access
+	nop
+	sfence.vma
+	lr.d a2, 0(x8)                         // Test load access
+	nop	
+	sfence.vma
+	sc.d t1, a2, 0(x8)                     // Test store access
+	nop
+
+# -------------------- Disable Pointer Masking (PMM) ---------------------------
+
+	LI a3, 0x000000000
+	csrw mseccfg, a3                      // Enable pointer masking with PMLEN = 16
+
+# -------------------- Disable Virtualization ---------------------------------
+
+	RVTEST_GOTO_MMODE                     // Switch back to Machine mode
+
+# -------------------- Signature Update ---------------------------------------
+
+	LI (t0, va_rvtest_sig_begin)           // Load virtual address of signature
+	LA (t1, rvtest_sig_begin)              // Load physical address of signature
+	sub t0, t0, t1                         // Calculate (VA - PA)
+	sub x13, x13, t0                       // Update signature register
+	addi x13, x13, REGWIDTH                // Adjust for register width
+	nop
+
+	LI (a4, 0x123)
+	RVTEST_SIGUPD(x13, a4)                 // Verify signature after virtualization disabled
+
+#endif
+
+# -----------------------------------------------------------------------------
+
+RVTEST_CODE_END
+RVMODEL_HALT
+
+RVTEST_DATA_BEGIN
+.align 12
+rvtest_data:
+	.dword 0xdeadbeefdeadbeef
+	.dword 0xdeadbeefdeadbeef
+	.dword 0xdeadbeefdeadbeef
+	.dword 0xdeadbeefdeadbeef
+#ifdef rvtest_strap_routine
+.align 12
+rvtest_slvl1_pg_tbl:
+        RVTEST_PTE_IDENT_MAP(0,LVLS,RVTEST_ALLPERMS)	
+rvtest_slvl2_pg_tbl:
+        RVTEST_PTE_IDENT_MAP(0,LVLS,RVTEST_ALLPERMS)
+rvtest_slvl3_pg_tbl:
+        RVTEST_PTE_IDENT_MAP(0,LVLS,RVTEST_ALLPERMS)
+rvtest_slvl4_pg_tbl:
+        RVTEST_PTE_IDENT_MAP(0,LVLS,RVTEST_ALLPERMS)	        
+#endif
+RVTEST_DATA_END
+RVMODEL_DATA_BEGIN
+rvtest_sig_begin:
+sig_begin_canary:
+CANARY;
+// test signatures initialization
+signature_x13_1:
+    .fill 256*(XLEN/64),4,0xcafebeef
+
+// trap signatures initialization
+#ifdef rvtest_mtrap_routine
+mtrap_sigptr:
+    .fill 256*(XLEN/64),4,0xdeadbeef
+#endif
+
+sig_end_canary:
+CANARY;
+rvtest_sig_end:
+RVMODEL_DATA_END