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ci: add float and double extension test to CI #470

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ci: add float and double extension test to CI #470

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e0987bc
ci: add float and double extension test to CI
jamesbeyond Jun 9, 2024
3fc093e
ci: fix extension name
jamesbeyond Jun 9, 2024
21b230a
update default ci with FD
jamesbeyond Jun 9, 2024
7137e17
made fix
jamesbeyond Jun 10, 2024
a2f5a26
make fix
jamesbeyond Jun 11, 2024
e24f180
renamed
jamesbeyond Jun 11, 2024
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6 changes: 3 additions & 3 deletions .github/isa_templates/RV32IFZicsr.yaml → .github/isa_templates/RV32IFDZicsr.yaml
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Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
hart_ids: [0]
hart0:
ISA: RV32IFZicsr
ISA: RV32IFDZicsr
physical_addr_sz: 32
User_Spec_Version: '2.3'
supported_xlen: [32]
misa:
reset-val: 0x40000120
reset-val: 0x40000128
rv32:
accessible: true
mxl:
Expand All @@ -23,7 +23,7 @@ hart0:
warl:
dependency_fields: []
legal:
- extensions[25:0] bitmask [0x0000120, 0x0000000]
- extensions[25:0] bitmask [0x0000128, 0x0000000]
wr_illegal:
- Unchanged

6 changes: 3 additions & 3 deletions .github/isa_templates/RV32IMCZicsr_Zifencei.yaml
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Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
hart_ids: [0]
hart0:
ISA: RV32IMCZicsr_Zifencei
ISA: RV32IMCFDZicsr_Zifencei
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ISA string should be RV32IMFDCZicsr_Zifencei, C appears after F and D in RISC-V ISA config strong.

physical_addr_sz: 32
User_Spec_Version: '2.3'
supported_xlen: [32]
misa:
reset-val: 0x40001104
reset-val: 0x4000112C
rv32:
accessible: true
mxl:
Expand All @@ -23,7 +23,7 @@ hart0:
warl:
dependency_fields: []
legal:
- extensions[25:0] bitmask [0x0001104, 0x0000000]
- extensions[25:0] bitmask [0x000112C, 0x0000000]
wr_illegal:
- Unchanged

6 changes: 3 additions & 3 deletions .github/isa_templates/RV64IFZicsr.yaml → .github/isa_templates/RV64IFDZicsr.yaml
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
hart_ids: [0]
hart0:
ISA: RV64IFZicsr
ISA: RV64IFDZicsr
physical_addr_sz: 32
User_Spec_Version: '2.3'
supported_xlen: [64]
misa:
reset-val: 0x8000000000000120
reset-val: 0x8000000000000128
rv64:
accessible: true
mxl:
Expand All @@ -23,7 +23,7 @@ hart0:
warl:
dependency_fields: []
legal:
- extensions[25:0] bitmask [0x0000120, 0x0000000]
- extensions[25:0] bitmask [0x0000128, 0x0000000]
wr_illegal:
- Unchanged

6 changes: 3 additions & 3 deletions .github/isa_templates/RV64IMCZicsr_Zifencei.yaml
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
hart_ids: [0]
hart0:
ISA: RV64IMCZicsr_Zifencei
ISA: RV64IMCFDZicsr_Zifencei
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ISA string should be RV64IMFDCZicsr_Zifencei, C appears after F and D in RISC-V ISA config strong.

physical_addr_sz: 32
User_Spec_Version: '2.3'
supported_xlen: [64]
misa:
reset-val: 0x8000000000001104
reset-val: 0x800000000000112C
rv64:
accessible: true
mxl:
Expand All @@ -23,7 +23,7 @@ hart0:
warl:
dependency_fields: []
legal:
- extensions[25:0] bitmask [0x0001104, 0x0000000]
- extensions[25:0] bitmask [0x000112C, 0x0000000]
wr_illegal:
- Unchanged

3 changes: 2 additions & 1 deletion .github/workflows/test.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,8 @@ jobs:
isa_group:
- RV32IMCZicsr_Zifencei
- RV64IMCZicsr_Zifencei

- RV32IFDZicsr
- RV64IFDZicsr

steps:

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