Correcting IO assertion macros

[dpetrisko]

Description

This PR corrects the IO assertion macros in TEST_CASE_F and TEST_CASE_FID. Currently, they call GPR comparison, but these are floating point test cases. This causes predictable errors when compiling with any reasonable implementation of RVMODEL_IO_ASSERT_GPR_EQ.

riscv-arch-test/riscv-test-suite/rv64i_m/D/src/fcvt.d.lu_b26-01.S:42: Error: illegal operands `ld t1,0x08(f20)'
...
TEST_FPIO_OP(fcvt.d.lu, f20, x19, dyn, 0, 0, x9, 0*8, x11, x1, x5,ld)
...
#define TEST_FPIO_OP( inst, destreg, freg, rm, fcsr_val, correctval, valaddr_reg, val_offset, flagreg, swreg, testreg, load_instr) \
    TEST_CASE_F(testreg, destreg, correctval, swreg, flagreg,        \
      LOAD_MEM_VAL(load_instr, valaddr_reg, freg, val_offset, testreg)  ;\
      li testreg, fcsr_val; csrw fcsr, testreg  ;\
      inst destreg, freg, rm            ;\
      csrr flagreg, fcsr            ;\
    )

Related Issues

NA

Ratified/Unratified Extensions

• Ratified
• Unratified

List Extensions

F,D

Reference Model Used

• SAIL
• Spike
• Other - < SPECIFY HERE >

Mandatory Checklist:

• All tests are compliant with the test-format spec present in this repo ?
• Ran the new tests on RISCOF with SAIL/Spike as reference model successfully ?
• Ran the new tests on RISCOF in coverage mode
• Link to Google-Drive folder containing the new coverage reports (See this for more info): < SPECIFY HERE >
• Link to PR in RISCV-ISAC from which the reports were generated : < SPECIFY HERE >
• Changelog entry created with a minor patch

Optional Checklist:

• RISCV-V CTG PR link if tests were generated using it : < SPECIFY HERE >
• Were the tests hand-written/modified ?
• Have you run these on any hard DUT model ? Please specify name and provide link if possible in the description
• If you have modified arch_test.h Please provide a detailed description of the changes in the Description section above.

[dpetrisko]

Not sure on the checklists here. Let me know if you need help from me on it, but it's a fairly trivial change that should not break anything™

[allenjbaum]

I'm a bit puzzled as to what is going on here, because I don't see the code you're fixing in the repo. The current version I see doesn't use RVMODEL_IO_ASSERT_SFPR_EQ, it uses RVMODEL_IO_ASSERT_GPR_EQ - which is wrong, but it isn't what this PR is updating. What is the source of this?
The current version of the repo already has this fix.

The correct fix for the first change would be to change it to be a model defined RVMODEL_IO_ASSERT_FPR_EQ, which should use the FLREG/FSREG macros that take into account the current FLEN, just as your fix (and other macros) does.

[allenjbaum]

This is correctr now

[allenjbaum]

This is correct now

[dpetrisko]

Thanks!