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Signed-off-by: S Pawan Kumar <[email protected]>
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@pawks
pawks authored Jan 9, 2023
2 parents 8129c4c + 933dddd commit 9a2dfae
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7 changes: 7 additions & 0 deletions CHANGELOG.md
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=======

## [3.5.3] - 2022-11-22
- Fix Canary definition according to sigalign.
- Fix SIGALIGN definition.
- Fix inconsistencies in tests.
- Add Zicsr to ISA in RV32 privilege tests
- Modify signature size requirement to multiple of 4.

## [3.5.2] - 2022-11-25
- adding a pull request template
- removed riscv-test-stats directory and migrated those to a gdrive folder [here](https://drive.google.com/drive/folders/1KBRy6OgxnOPTDgyfJDj0gcMi5VdMLtVo?usp=share_link)
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2 changes: 1 addition & 1 deletion riscv-test-suite/env/arch_test.h
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Expand Up @@ -171,6 +171,7 @@
#define SREG sq
#define LREG lq
#define XLEN_WIDTH 7
#define LREGWU lwu
#endif

#if FLEN==32
Expand All @@ -187,7 +188,6 @@
#define FREGWIDTH 16
#endif


#if SIGALIGN==8
#define CANARY \
.dword 0x6F5CA309E7D4B281
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7 changes: 3 additions & 4 deletions riscv-test-suite/rv32i_m/C/src/cebreak-01.S
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Expand Up @@ -6,13 +6,10 @@
// This assembly file tests the c.ebreak instruction of the RISC-V C extension.
//


#define rvtest_mtrap_routine

#include "model_test.h"
#include "arch_test.h"

RVTEST_ISA("RV32IC")
RVTEST_ISA("RV32IC_Zicsr")

# Test code region
.section .text.init
Expand Down Expand Up @@ -64,8 +61,10 @@ CANARY;
test_A_res:
.fill 2, 4, 0xdeadbeef

#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 4, 4, 0xdeadbeef
#endif

#ifdef rvtest_gpr_save
gpr_save:
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5 changes: 5 additions & 0 deletions riscv-test-suite/rv32i_m/Zifencei/src/Fencei.S
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Expand Up @@ -94,6 +94,11 @@ CANARY;
test_A_res:
.fill 4, 4, 0xdeadbeef

#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 4, 4, 0xdeadbeef
#endif

#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32), 4, 0xdeadbeef
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7 changes: 6 additions & 1 deletion riscv-test-suite/rv32i_m/privilege/src/ebreak.S
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Expand Up @@ -9,7 +9,7 @@
#include "model_test.h"
#include "arch_test.h"

RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")

# Test code region
.section .text.init
Expand All @@ -25,11 +25,14 @@ RVTEST_CODE_BEGIN
LA( x1,test_A_res)

LI( x2,0x11111111)
.option push;
.option norvc;
ebreak
nop
nop
sw x0, 0(x1)
sw x2, 4(x1)
.option pop;

RVMODEL_IO_WRITE_STR(x30, "# Test part A - test EBREAK\n");

Expand All @@ -56,8 +59,10 @@ CANARY;
test_A_res:
.fill 2, 4, 0xdeadbeef

#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 4, 4, 0xdeadbeef
#endif

#ifdef rvtest_gpr_save
gpr_save:
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/src/ecall.S
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Expand Up @@ -9,7 +9,7 @@
#include "model_test.h"
#include "arch_test.h"

RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")

# Test code region
.section .text.init
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S
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Expand Up @@ -17,7 +17,7 @@
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")

.section .text.init
.globl rvtest_entry_point
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/src/misalign-bge-01.S
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Expand Up @@ -17,7 +17,7 @@
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")

.section .text.init
.globl rvtest_entry_point
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/src/misalign-bgeu-01.S
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Expand Up @@ -17,7 +17,7 @@
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")

.section .text.init
.globl rvtest_entry_point
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/src/misalign-blt-01.S
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Expand Up @@ -17,7 +17,7 @@
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")

.section .text.init
.globl rvtest_entry_point
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/src/misalign-bltu-01.S
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Expand Up @@ -17,7 +17,7 @@
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")

.section .text.init
.globl rvtest_entry_point
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/src/misalign-bne-01.S
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Expand Up @@ -17,7 +17,7 @@
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")

.section .text.init
.globl rvtest_entry_point
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/src/misalign-jal-01.S
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Expand Up @@ -17,7 +17,7 @@
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")

.section .text.init
.globl rvtest_entry_point
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/src/misalign-lh-01.S
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Expand Up @@ -17,7 +17,7 @@
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")

.section .text.init
.globl rvtest_entry_point
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/src/misalign-lhu-01.S
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Expand Up @@ -17,7 +17,7 @@
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")

.section .text.init
.globl rvtest_entry_point
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/src/misalign-lw-01.S
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Expand Up @@ -17,7 +17,7 @@
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")

.section .text.init
.globl rvtest_entry_point
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/src/misalign-sh-01.S
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Expand Up @@ -17,7 +17,7 @@
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")

.section .text.init
.globl rvtest_entry_point
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/src/misalign-sw-01.S
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Expand Up @@ -17,7 +17,7 @@
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")

.section .text.init
.globl rvtest_entry_point
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2 changes: 1 addition & 1 deletion riscv-test-suite/rv32i_m/privilege/src/misalign2-jalr-01.S
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Expand Up @@ -17,7 +17,7 @@
//
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I")
RVTEST_ISA("RV32I_Zicsr")

.section .text.init
.globl rvtest_entry_point
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8 changes: 4 additions & 4 deletions riscv-test-suite/rv64i_m/C/src/cebreak-01.S
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Expand Up @@ -7,12 +7,10 @@
// This assembly file tests the c.ebreak instruction of the RISC-V C extension.
//

#define rvtest_mtrap_routine

#include "model_test.h"
#include "arch_test.h"

RVTEST_ISA("RV64IC")
RVTEST_ISA("RV64IC_Zicsr")

# Test code region
.section .text.init
Expand Down Expand Up @@ -63,8 +61,10 @@ CANARY;
test_A_res:
.fill 2, 4, 0xdeadbeef

#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 4, 4, 0xdeadbeef
.fill 8, 4, 0xdeadbeef
#endif

#ifdef rvtest_gpr_save
gpr_save:
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5 changes: 5 additions & 0 deletions riscv-test-suite/rv64i_m/Zifencei/src/Fencei.S
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Expand Up @@ -91,6 +91,11 @@ CANARY;
test_A_res:
.fill 4, 4, 0xdeadbeef

#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 8, 4, 0xdeadbeef
#endif

#ifdef rvtest_gpr_save
gpr_save:
.fill 32*(XLEN/32), 4, 0xdeadbeef
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8 changes: 6 additions & 2 deletions riscv-test-suite/rv64i_m/privilege/src/ebreak.S
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Expand Up @@ -26,12 +26,14 @@ RVTEST_CODE_BEGIN
LA( x1,test_A_res)

LI( x2,0x11111111)
.option push;
.option norvc;
ebreak
nop
nop
sw x0, 0(x1)
sw x2, 4(x1)

.option pop;
RVMODEL_IO_WRITE_STR(x30, "# Test part A - test EBREAK\n");

RVMODEL_IO_WRITE_STR(x30, "# Test End\n")
Expand All @@ -57,8 +59,10 @@ CANARY;
test_A_res:
.fill 2, 4, 0xdeadbeef

#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 4, 4, 0xdeadbeef
.fill 8, 4, 0xdeadbeef
#endif

#ifdef rvtest_gpr_save
gpr_save:
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4 changes: 3 additions & 1 deletion riscv-test-suite/rv64i_m/privilege/src/ecall.S
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Expand Up @@ -57,8 +57,10 @@ CANARY;
test_A_res:
.fill 2, 4, 0xdeadbeef

#ifdef rvtest_mtrap_routine
mtrap_sigptr:
.fill 4, 4, 0xdeadbeef
.fill 8, 4, 0xdeadbeef
#endif

#ifdef rvtest_gpr_save
gpr_save:
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4 comments on commit 9a2dfae

@allenjbaum
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Lots of instructions won't define mtrap_sigptr unless mtrap_routine is defined - and I can't remember: does it get defined somewhere else?
Because the reg_save area has one word initialized to the label, and things will break if it isn't defined (at least, that was the case once upon a time)

@pawks
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@pawks pawks commented on 9a2dfae Jan 10, 2023

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Lots of instructions won't define mtrap_sigptr unless mtrap_routine is defined - and I can't remember: does it get defined somewhere else? Because the reg_save area has one word initialized to the label, and things will break if it isn't defined (at least, that was the case once upon a time)

I don't see this problem anymore. I believe it has been fixed. We can put the mtrap_sigptr labbels inside the ifdefs and since all the code which refers to that is also inside the same ifdef, it works without any errors.

@allenjbaum
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the mtrap_sigptr labels are used inside macros, and those instances are not inside ifdefs.
The macros won't be instantiated unless #ifdef mtrap_routine is defined - but I'm unsure if the compiler is smart enough to figure that out or not.
The next version of the trap handler removes all the LAs outside of the prolog and epilog (which are performed in M-mode) require additional uses of mtrap_sigptr to calculate regular and trap signature sizes.

@pawks
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@pawks pawks commented on 9a2dfae Jan 12, 2023

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the mtrap_sigptr labels are used inside macros, and those instances are not inside ifdefs. The macros won't be instantiated unless #ifdef mtrap_routine is defined - but I'm unsure if the compiler is smart enough to figure that out or not. The next version of the trap handler removes all the LAs outside of the prolog and epilog (which are performed in M-mode) require additional uses of mtrap_sigptr to calculate regular and trap signature sizes.

All of this is being handled in the preprocessing phase of the compiler. So as long as the macro instantiation is surrounded by the ifdef it will work fine.

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