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modificatios: various typo fixes, LI/LA changes, and un-bit-reversing…
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… the SET/CODE_REL_TVAL_MSKs
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@UmerShahidengr
UmerShahidengr committed Aug 19, 2022
1 parent 95a5c01 commit 4d78fe3
Showing 1 changed file with 52 additions and 41 deletions.
93 changes: 52 additions & 41 deletions riscv-test-suite/env/arch_test.h
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Original file line number Diff line number Diff line change
Expand Up @@ -62,19 +62,14 @@
RVMODEL_CLR_[M/V/S]_[SW/TIMTER/EXT]_INT
rvtest_[M/V/S]trap_routine
GOTO_[M/S/U]MODE, INSTANTIATE_MODE_MACRO (prolog/handler/epilog/savearea)
The following macro is optional, and defaults to fence.i if not defined
RVMODEL.FENCEI
The following variables are used if interrupt tests are enabled (defaulted if not defined):
NUM_SPECD_INTCAUSES
The following variables are optional if exception tests are enabled (defaulted if not defined):
DATA_REL_TVAL_MSK CODE_REL_TVAL_MSK
The following variables are optional:
rvtest_gpr_save: if defined, stores GPR contents into signature at test end (for debug)
The following labels are required and defined by required macros:
rvtest_code_begin: defined by RVTEST_CODE_BEGIN macro (boot code can precede this)
rvtest_code_end: defined by RVTEST_CODE_END macro (trap handlers follow this)
Expand All @@ -84,10 +79,8 @@
rvtest_sig_end: defined by RVTEST_SIG_END macro (before RVMODEL_DATA_END) defines signature end
rvtest_sroot_pg_tbl: defined by RVTEST_PTE_IDENT_MAP macro inside RVTEST_DATA_BEGIN if Smode implemented
rvtest_vroot_pg_tbl: defined by RVTEST_PTE_IDENT_MAP macro inside RVTEST_DATA_BEGIN if VSmode implemented
labels/variables that must be defined by the DUT in model specific macros or #defines
mtrap_sigptr: defined by test if traps are possible, else is defaulted
*/
// don't put C-style macros (#define xxx) inside assembly macros; C-style is evaluated before assembly

Expand Down Expand Up @@ -123,13 +116,13 @@

// **Note** that this is different that previous DATA_REL_TVAL_MASK! This is the OR of Code_Rel+Data_Rel
// 0xDF0D corresponds to causes 0..7,12,13,15 (inst misalgn/illop/access,page fault,bkpt, ld/st misalgn/access/pg fault, ecall )
#ifndef TVAL_LD_MSK
#define LD_TVAL_MSK 0xDF0D << (REGWIDTH*8-16)
#ifndef SET_REL_TVAL_MSK
#define SET_REL_TVAL_MSK 0xB0FF << (REGWIDTH*8-16)
#endif

// 0xD008 corresponds to causes 0,1,3,12 (inst misalign, access,page fault, breakpt)
#ifndef CODE_REL_TVAL_MSK
#define CODE_REL_TVAL_MSK 0xD008 << (REGWIDTH*8-16)
#define CODE_REL_TVAL_MSK 0x100B
#endif

#ifndef GOTO_M_OP
Expand Down Expand Up @@ -243,17 +236,39 @@
// could be optimized further by fusing contiguous shifts into a single shift.

/**** fixed length LI macro ****/
#define LI(reg,val) ;\
.option push ;\
.option norvc ;\
li reg,val ;\
.option pop;
#define LI(reg,val) ;\
.option push ;\
.option norvc ;\
.if ((((val>>11)+1)>>1)==0) ;\
addi reg,x0,val /* <=12bit signed imm */ ;\
.elseif ((((val>>31)+1)>>1)==0) ;\
li reg, val /* <=32bit, will be auipc/addi pair */ ;\
.elseif (((val-1)&val) ==0) /* single bit optimization */ ;\
.set shamt, XLEN-12 ;\
.rept XLEN-12 ;\
.if (val>>shamt)==1 ;\
addi reg, x0, 1 ;\
slli reg, reg, shamt;\
.endif ;\
.set shamt, shamt+1 ;\
.endr ;\
.else ;\
.option pop ;\
.align UNROLLSZ ;\
.option push ;\
.option norvc ;\
li reg,val ;\
.align UNROLLSZ ;\
.endif ;\
.option pop;

/**** fixed length LA macro ****/
#define LA(reg,val) ;\
.option push ;\
.option norvc ;\
la reg,val ;\
.option push ;\
.option norvc ;\
.align UNROLLSZ ;\
la reg,val ;\
.align UNROLLSZ ;\
.option pop ;

/*****************************************************************/
Expand Down Expand Up @@ -347,10 +362,10 @@

/******************************************************************************/
/**** this is a helper macro that creates CSR aliases so code that ****/
/**** accesses CSRs in different modes can share the code ****/
/**** accesses CSRs when V=1 in different modes can share the code ****/
/******************************************************************************/

.macro XCSR_RENAME __MODE__ // enable CSR names to be parameterized.
.macro XCSR_RENAME __MODE__ // enable CSR names to be parameterized.
.if ((\__MODE__ == S) | (\__MODE__ == V))
.set CSR_XSTATUS, CSR_SSTATUS
.set CSR_XEDELEG, CSR_SEDELEG
Expand Down Expand Up @@ -467,9 +482,7 @@
rvtest_sig_end: ;\
signature_end: /* redundant for bkwards compatibility */ ;\
RVMODEL_DATA_END /* model specific stuff
//#define rvtest_sig_sz (rvtest_sig_end - rvtest_sig_begin) not currently used
/***************************************************************************************/
/**** At end of test, this code is entered. It diverts the Mmode trampoline to code ****/
/**** that follows this, executes an op illegal in any non-Mmode, then restores the ****/
Expand Down Expand Up @@ -564,7 +577,7 @@ rvtest_sig_end: ;\
li t4, 1 /* optimize for single bit */
slli t4, t4, 32+MPV_LSB /* val for v only */
.endif
csrs t4, CSR_MSTATUS /* set correct mode and Vbit */
csrs CSR_MSTATUS, t4 /* set correct mode and Vbit */
.endif
.endif
/**** mstatus MPV and PP now set up to desired mode ****/
Expand Down Expand Up @@ -879,8 +892,6 @@ common_\__MODE__\()entry:
//------this should be atomic-------------------------------------
LREG t1, 0(t3) // get the trap signature pointer (initialized to mtrap_sigptr)
add t4, t1, t2 // pre-inc pointer so nested traps don't corrupt signature queue
// addi t3, t3, REGWIDTH

SREG t4, 0(t3) // and save new value (old value is still in t1)
//------end atomic------------------------------------------------
#ifdef rvtest_sig_end // if not defined, we can't test for overrun
Expand Down Expand Up @@ -924,8 +935,7 @@ adj_\__MODE__\()epc: // adj mepc so there is padding after op, and its 8B alig

/******************************************************************************/
/* Calculate relative mtval if it’s an addr (by code_begin or data_begin amt) */
/* Which to use is defined by model-defined bit-reversed mask values that are */
/* indexed by xcause value (so mcause==0 bit is in MSB (bit63/31 for RV64/32) */
/* Model-defined mask values (indexed by xcause value) select which to use */
/* Enter with rvtest_code_begin (which is start of actual test) in t3 */
/* if illegal op, load opcode from mtval (if !=0) or from istream (if ==0) */
/******************************************************************************/
Expand All @@ -935,13 +945,15 @@ adj_\__MODE__\()tval:
csrr t4, CSR_XCAUSE
csrr t6, CSR_XTVAL

LI( t5, LD_TVAL_MSK)
sll t5, t5, t4 // put mcause bit# in MSB
LI( t5, SET_REL_TVAL_MSK)
srl t5, t5, t4 // put mcause bit# into LSB if not bit reversed (remove above)
slli t5, t5, XLEN-1 // put mcause bit# into MSB
bge t5, x0, no_\__MODE__\()adj // if MSB=0, no correction needed
code_\__MODE__\()adj:
LI( t5, CODE_REL_TVAL_MSK) // trap#s 12, 3,1,0, -- code relative traps
sll t5, t5, t4 // put mcause bit# in MSB
bltz t5, sv_\__MODE__\()tval // if MSB=1, use code_adj in t3
srl t5, t5, t4 // put mcause bit# into LSB if not bit reversed (remove above)
slli t5, t5, XLEN-1 // put mcause bit# into MSB
bltz t5, sv_\__MODE__\()tval // if MSB=1, use code_adj in t3, else use data_adj

/********************************?FIXME?***************************************/
/* FIXME?? are there multiple cases where the address must be relocated with */
Expand All @@ -950,14 +962,16 @@ code_\__MODE__\()adj:
/******************************************************************************/

/**** FIXME: these begin/end addresses may not match how RVMODEL_DATA_BEGIN/END set the address ****/
sigdata_\__MODE__\()adj: // only possibilities left are illop, testdata or sigdata
// LA( t3, rvtest_sig_end) // after sig area, skip
// bge t6, t3, tstdata_\__MODE__\()adj
// LA( t3, rvtest_sig_begin)
// bge t6, t3, adj_\__MODE__\()tval // inside sig area, lv rvtest_sig_begin as adjustment amt
dat_rgn_\__MODE__\()adj: // only possibilities left are illop, testdata or sigdata
LA( t3, rvtest_data_end)
bge t6, t3, tstdata_\__MODE__\()adj // after data area, must be sig, adj according to isg label
LA( t3, rvtest_data_begin)
bge t6, t3, adj_\__MODE__\()tval // inside data area, lv rvtest_data_begin as adjustment amt
sigdata_\__MODE__\()adj:
LA( t3, mtrap_sigptr) // adj assuming sig_region access
tstdata_\__MODE__\()adj:
LA( t3, rvtest_data_begin) // adjustment assuming access is to a data region ***FIXME: not fixed relative to data!!!!!!
addi t4, t4, -2 // check if mcause==2 (illegal op)
LA( t3, rvtest_data_begin) // adjustment assuming access is to a data region ***FIXME: not fixed relative to data!!!!!!
addi t4, t4, -2 // check if mcause==2 (illegal op, neither data nor code relative))
bnez t4, sv_\__MODE__\()tval // not illegal op, use data relative amt

/******************************************************************************/
Expand Down Expand Up @@ -986,13 +1000,10 @@ ill_\__MODE__\()op:
sv_\__MODE__\()tval: // adjustment amt is in t3, tval or opcode in t2
sub t6, t6, t3 // perform mtval adjust by either code or data position or zero in t3
no_\__MODE__\()adj: // For Illegal op handling or tval not loaded - opcode not address
// Commenting the next line to stop printing 4th sig value (int ID)
SREG t6, 3*REGWIDTH(t1) // save 4th sig value, (rel mtval) into trap signature area
.if (\__MODE__\() == M)
.ifdef __H_EXT__
csrr t2, CSR_MTVAL2
// THIS NEXT LINE WILL BECOME THE 4th SIGNATURE VALUE IF ABOVE LINES WILL BE COMMENTED OUT
// I HAVE NOT CHANGED THE OFFSET YET, BUT IT WILL BE CHANGED AFTER MAKING DECISION ON 4th SIGNATURE VALUE
SREG t2, 4*REGWIDTH(t1) // store 5th sig value, only if mmode handler and VS mode exists
csrr t2, CSR_MTINST
SREG t2, 5*REGWIDTH(t1) // store 6th sig value, only if mmode handler and VS mode exists
Expand Down

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