Add Zicbom and Zicbop extension

coverage/cmo/cbom.cgf

@@ -0,0 +1,37 @@
+# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore
+
+cbo.clean:
+    config:
+      - check ISA:=regex(.*I.*Zicbom.*Zicsr.*)
+    mnemonics:
+      cbo.clean: 0
+    rs1:
+      <<: *all_regs_mx0
+    val_comb:
+      <<: [*base_rs1val_unsgn]
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn]
+
+cbo.flush:
+    config:
+      - check ISA:=regex(.*I.*Zicbom.*Zicsr.*)
+    mnemonics:
+      cbo.flush: 0
+    rs1:
+      <<: *all_regs_mx0
+    val_comb:
+      <<: [*base_rs1val_unsgn]
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn]
+
+cbo.inval:
+    config:
+      - check ISA:=regex(.*I.*Zicbom.*Zicsr.*)
+    mnemonics:
+      cbo.inval: 0
+    rs1:
+      <<: *all_regs_mx0
+    val_comb:
+      <<: [*base_rs1val_unsgn]
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn]

coverage/cmo/cbop.cgf

@@ -0,0 +1,37 @@
+# For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore
+
+prefetch.i:
+    config:
+      - check ISA:=regex(.*I.*Zicbop.*Zicsr.*)
+    mnemonics:
+      prefetch.i: 0
+    rs1:
+      <<: *all_regs
+    val_comb:
+      <<: [*zicbop_ifmt_val_comb_unsgn, *base_rs1val_unsgn, *ifmt_base_immval11_5_sgn]
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn, *ifmt_immval_walking_11_5]
+
+prefetch.r:
+    config:
+      - check ISA:=regex(.*I.*Zicbop.*Zicsr.*)
+    mnemonics:
+      prefetch.r: 0
+    rs1:
+      <<: *all_regs
+    val_comb:
+      <<: [*zicbop_ifmt_val_comb_unsgn, *base_rs1val_unsgn, *ifmt_base_immval11_5_sgn]
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn, *ifmt_immval_walking_11_5]
+
+prefetch.w:
+    config:
+      - check ISA:=regex(.*I.*Zicbop.*Zicsr.*)
+    mnemonics:
+      prefetch.w: 0
+    rs1:
+      <<: *all_regs
+    val_comb:
+      <<: [*zicbop_ifmt_val_comb_unsgn, *base_rs1val_unsgn, *ifmt_base_immval11_5_sgn]
+      abstract_comb:
+        <<: [*rs1val_walking_unsgn, *ifmt_immval_walking_11_5]

coverage/rv32i_cbo.cgf → coverage/cmo/cboz.cgf

@@ -1,6 +1,6 @@
 # For Licence details look at https://github.com/riscv-software-src/riscv-ctg/-/blob/master/LICENSE.incore
 
-cbozero:
+cbo.zero:
     config:
       - check ISA:=regex(.*I.*Zicboz.*Zicsr.*)
     mnemonics:

coverage/dataset.cgf

@@ -305,7 +305,7 @@ datasets:
   r0fmt_op_comb: &r0fmt_op_comb
     'rs1 == 0': 0
     'rs1 != 0': 0
-  
+
   base_rs1val_sgn: &base_rs1val_sgn
     'rs1_val == (-2**(xlen-1))': 0
     'rs1_val == 0': 0
@@ -317,7 +317,7 @@ datasets:
     'rs1_val == 0 and rs2_val == 0': 0
     'rs1_val == (2**(xlen-1)-1) and rs2_val == 0': 0
     'rs1_val == 1 and rs2_val == 0': 0
-  
+
   base_rs2val_sgn: &base_rs2val_sgn
     'rs2_val == (-2**(xlen-1))': 0
     'rs2_val == 0': 0
@@ -330,12 +330,11 @@ datasets:
     'rs3_val == (2**(xlen-1)-1)': 0
     'rs3_val == 1': 0
 
-
   base_rs1val_unsgn: &base_rs1val_unsgn
     'rs1_val == 0': 0
     'rs1_val == (2**(xlen)-1)': 0
     'rs1_val == 1': 0
-  
+
   base_rs2val_unsgn: &base_rs2val_unsgn
     'rs2_val == 0': 0
     'rs2_val == (2**(xlen)-1)': 0
@@ -356,7 +355,7 @@ datasets:
 
   div_corner_case: &div_corner_case
     'rs1_val == -(2**(xlen-1)) and rs2_val == -0x01': 0
-  
+
   rfmt_val_comb_unsgn: &rfmt_val_comb_unsgn
     'rs1_val > 0 and rs2_val > 0': 0
     'rs1_val == rs2_val and rs1_val > 0 and rs2_val > 0': 0
@@ -374,12 +373,23 @@ datasets:
     'rs1_val == imm_val and rs1_val > 0 and imm_val > 0': 0
     'rs1_val != imm_val and rs1_val > 0 and imm_val > 0': 0
 
+  zicbop_ifmt_val_comb_unsgn: &zicbop_ifmt_val_comb_unsgn
+    'rs1_val == imm_val and rs1_val == 0': 0
+    'rs1_val < imm_val and rs1_val != 0': 0
+    'rs1_val > imm_val and imm_val == 0': 0
+
   ifmt_base_immval_sgn: &ifmt_base_immval_sgn
     'imm_val == (-2**(12-1))': 0
     'imm_val == 0': 0
     'imm_val == (2**(12-1)-1)': 0
     'imm_val == 1': 0
 
+  ifmt_base_immval11_5_sgn: &ifmt_base_immval11_5_sgn
+    'imm_val == (-2**(7-1)) << 5': 0
+    'imm_val == 0': 0
+    'imm_val == (2**(7-1)-1) << 5': 0
+    'imm_val == 1<<5': 0
+
   ifmt_base_immval_sgn_len: &ifmt_base_immval_sgn_len
     'imm_val == (-2**(ceil(log(xlen,2))-1))': 0
     'imm_val == 0': 0
@@ -445,7 +455,7 @@ datasets:
     'rs1_val > rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0
     'rs1_val < rs2_val and imm_val > 0 and imm_val & 0x03 == 0': 0
     'rs1_val < rs2_val and imm_val < 0 and imm_val & 0x03 == 0': 0
-  
+
   bfmt_base_branch_val_align_unsgn: &bfmt_base_branch_val_align_unsgn
     'rs1_val > 0 and rs2_val > 0': 0
     'rs1_val > 0 and rs2_val > 0 and rs1_val == rs2_val and imm_val > 0': 0
@@ -490,12 +500,17 @@ datasets:
     'walking_ones("imm_val", 5, False)': 0
     'walking_zeros("imm_val", 5, False)': 0
     'alternate("imm_val", 5, False)': 0
-
+
+  ifmt_immval_walking_11_5: &ifmt_immval_walking_11_5
+    'walking_ones("imm_val", 7, signed = True, scale_func = lambda x: x << 5)': 0
+    'walking_zeros("imm_val", 7, signed = True, scale_func = lambda x: x << 5)': 0
+    'alternate("imm_val", 7, signed = True, scale_func = lambda x: x << 5)': 0
+
   rs1val_walking_unsgn: &rs1val_walking_unsgn
     'walking_ones("rs1_val", xlen,False)': 0
     'walking_zeros("rs1_val", xlen,False)': 0
     'alternate("rs1_val",xlen,False)': 0
-  
+
   rs2val_walking_unsgn: &rs2val_walking_unsgn
     'walking_ones("rs2_val", xlen,False)': 0
     'walking_zeros("rs2_val", xlen,False)': 0
@@ -509,7 +524,7 @@ datasets:
     'walking_ones("imm_val", 6)': 0
     'walking_zeros("imm_val", 6)': 0
     'alternate("imm_val",6)': 0
-  
+
   ifmt_immval_walking_unsgn: &ifmt_immval_walking_unsgn
     'walking_ones("imm_val", 12,False)': 0
     'walking_zeros("imm_val", 12,False)': 0

riscv-ctg/CHANGELOG.md

@@ -7,7 +7,7 @@ Only when a release to the main branch is done, the contents of the WIP-DEV are
 versioned header while the `WIP-DEV` is left empty
 
 ## [WIP-DEV]
-- Added support for zicboz extexnsion
+- Added support for zicboz/zicbom/zicbop extexnsion
 
 ## [0.12.2] - 2024-03-06
 - Add Zfa support. (PR#60)

riscv-ctg/riscv_ctg/data/template.yaml

@@ -10424,15 +10424,120 @@ cbo.zero:
     sz: 'RVMODEL_CBZ_BLOCKSIZE'
   xlen: [32,64]
   isa:
-    - IZicbozZicsr
+    - IZicboz_Zicsr
   formattype: 'zformat'
   rs1_op_data: *all_regs_mx0
-  rs1_val_data: 'gen_usign_dataset(12)'
+  rs1_val_data: 'gen_usign_dataset(12) + gen_sp_dataset(xlen,False)'
   template: |-
 
     // $comment
     // opcode: $inst ; op1:$rs1; op1val:$rs1_val
-    TEST_CBO_ZERO($swreg,$rs1,$inst,$rs1_val)
+    TEST_CBO($swreg,$rs1,$inst,$rs1_val)
+
+cbo.clean:
+  std_op:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  isa:
+    - IZicbom_Zicsr
+  formattype: 'zformat'
+  rs1_op_data: *all_regs
+  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op1val:$rs1_val
+    TEST_CBO($swreg,$rs1,$inst,$rs1_val)
+
+cbo.flush:
+  std_op:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  isa:
+    - IZicbom_Zicsr
+  formattype: 'zformat'
+  rs1_op_data: *all_regs
+  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op1val:$rs1_val
+    TEST_CBO($swreg,$rs1,$inst,$rs1_val)
+
+cbo.inval:
+  std_op:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  isa:
+    - IZicbom_Zicsr
+  formattype: 'zformat'
+  rs1_op_data: *all_regs
+  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; op1val:$rs1_val
+    TEST_CBO($swreg,$rs1,$inst,$rs1_val)
+
+prefetch.i:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZicbop_Zicsr
+  formattype: 'iformat'
+  rs1_op_data: *all_regs
+  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,False)'
+  imm_val_data: '[v << 5 for v in gen_sign_dataset(7)]'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; op2val:$imm_val
+    TEST_PREFETCH($swreg,$rs1,$inst,$rs1_val,$imm_val)
+
+prefetch.r:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZicbop_Zicsr
+  formattype: 'iformat'
+  rs1_op_data: *all_regs
+  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  imm_val_data: '[v << 5 for v in gen_sign_dataset(7)]'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; op2val:$imm_val
+    TEST_PREFETCH($swreg,$rs1,$inst,$rs1_val,$imm_val)
+
+prefetch.w:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32,64]
+  std_op:
+  isa:
+    - IZicbop_Zicsr
+  formattype: 'iformat'
+  rs1_op_data: *all_regs
+  rs1_val_data: 'gen_usign_dataset(xlen) + gen_sp_dataset(xlen,True)'
+  imm_val_data: '[v << 5 for v in gen_sign_dataset(7)]'
+  template: |-
+
+    // $comment
+    // opcode: $inst ; op1:$rs1; dest:$rd; op1val:$rs1_val; op2val:$imm_val
+    TEST_PREFETCH($swreg,$rs1,$inst,$rs1_val,$imm_val)
 
 amoadd.w:
   sig:

riscv-ctg/riscv_ctg/generator.py

@@ -172,7 +172,7 @@ def get_rm(opcode):
     'prrformat': '["rs1_val", "rs2_val"]',
     'prrrformat': "['rs1_val', 'rs2_val' , 'rs3_val']",
     'dcasrformat': '["rs1_val", "rs2_val"]',
-    'zformat': ['rs1']
+    'zformat': "['rs1_val']"
 }
 ''' Dictionary mapping instruction formats to operand value variables used by those formats '''
 
@@ -1134,6 +1134,7 @@ def swreg(self, instr_dict):
         else:
             FLEN = 0
         XLEN = max(self.opnode['xlen'])
+        RVMODEL_CBZ_BLOCKSIZE = XLEN
         SIGALIGN = max(XLEN,FLEN)/8
         stride_sz = eval(suffix)
         for instr in instr_dict:

riscv-test-suite/env/test_macros.h

@@ -769,14 +769,21 @@ nop					;\
 csrr flagreg, fcsr			;\
 RVTEST_SIGUPD_F(swreg,destreg,flagreg) 
 
-#define TEST_CBO_ZERO(swreg,rs1,inst,imm_val)                               ;\
-LI(rs1,imm_val&(RVMODEL_CBZ_BLOCKSIZE-1))                                   ;\
+#define TEST_CBO(swreg,rs1,inst,rs1_val)                                    ;\
+LI(rs1,rs1_val&(RVMODEL_CBZ_BLOCKSIZE-1))                                   ;\
 add rs1,rs1,swreg                                                           ;\
 inst (rs1)                                                                  ;\
 nop                                                                         ;\
 nop                                                                         ;\
 ADDI(swreg, swreg, RVMODEL_CBZ_BLOCKSIZE)
 
+#define TEST_PREFETCH(swreg,rs1,inst,rs1_val,imm_val)                       ;\
+LI(rs1,rs1_val)                                                             ;\
+inst imm_val(rs1)                                                           ;\
+nop                                                                         ;\
+nop                                                                         ;\
+ADDI(swreg, swreg, RVMODEL_CBZ_BLOCKSIZE)
+
 #define TEST_CSR_FIELD(ADDRESS,TEMP_REG,MASK_REG,NEG_MASK_REG,VAL,DEST_REG,OFFSET,BASE_REG) ;\
     LI(TEMP_REG,VAL)			;\
     and TEMP_REG,TEMP_REG,MASK_REG	;\