Merge branch 'dev' into fix-ctg-reproduce

coverage/cgfs_fext/RV32Zcd/fld.cgf

@@ -0,0 +1,67 @@
+c.fld:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*C.*)
+    mnemonics: 
+      c.fld: 0
+    rs1: 
+      <<: *c_regs
+    rd: 
+      <<: *c_fregs
+    op_comb: 
+        'rs1 != rd': 0
+    val_comb:
+        'imm_val > 0  and fcsr == 0': 0
+        'imm_val == 0 and fcsr == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0
+
+c.fsd:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*C.*)
+    opcode: 
+      c.fsd: 0
+    rs1: 
+      <<: *c_regs
+    rs2: 
+      <<: *c_fregs
+    op_comb: 
+        'rs1 != rs2': 0
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0
+
+c.fldsp:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*C.*)
+    opcode: 
+      c.fldsp: 0
+    rd: 
+      <<: *all_fregs
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0
+
+c.fsdsp:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*C.*)
+    opcode: 
+      c.fsdsp: 0
+    rs2: 
+      <<: *all_fregs
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0

coverage/cgfs_fext/RV32Zcf/flw.cgf

@@ -0,0 +1,65 @@
+c.flw:
+    config: 
+      - check ISA:=regex(.*I.*F.*C.*)
+    mnemonics: 
+      c.flw: 0
+    rs1: 
+      <<: *c_regs
+    rd: 
+      <<: *c_fregs
+    val_comb:
+        'imm_val > 0  and fcsr == 0': 0
+        'imm_val == 0 and fcsr == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0
+          'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0
+          'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0
+
+c.flwsp:
+    config: 
+      - check ISA:=regex(.*I.*F.*C.*)
+    opcode: 
+      c.flwsp: 0
+    rd: 
+      <<: *c_fregs
+    val_comb:
+        'imm_val > 0  and fcsr == 0': 0
+        'imm_val == 0 and fcsr == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0
+          'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0
+          'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0
+
+c.fsw:
+    config: 
+      - check ISA:=regex(.*I.*F.*C.*)
+    opcode: 
+      c.fsw: 0
+    rs1: 
+      <<: *c_regs
+    rs2: 
+      <<: *c_fregs
+    op_comb: 
+        'rs1 != rs2': 0
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",5,False, scale_func = lambda x: x*4)': 0
+          'walking_zeros("imm_val",5,False, scale_func = lambda x: x*4)': 0
+          'alternate("imm_val",5, False,scale_func = lambda x: x*4)': 0
+
+c.fswsp:
+    config: 
+      - check ISA:=regex(.*I.*F.*C.*)
+    opcode: 
+      c.fswsp: 0
+    rs2: 
+      <<: *c_fregs
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",6,False, scale_func = lambda x: x*4)': 0
+          'walking_zeros("imm_val",6,False, scale_func = lambda x: x*4)': 0
+          'alternate("imm_val",6, False,scale_func = lambda x: x*4)': 0

coverage/cgfs_fext/RV64Zcd/fld.cgf

@@ -0,0 +1,67 @@
+c.fld:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*C.*)
+    mnemonics: 
+      c.fld: 0
+    rs1: 
+      <<: *c_regs
+    rd: 
+      <<: *c_fregs
+    op_comb: 
+        'rs1 != rd': 0
+    val_comb:
+        'imm_val > 0  and fcsr == 0': 0
+        'imm_val == 0 and fcsr == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0
+
+c.fsd:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*C.*)
+    opcode: 
+      c.fsd: 0
+    rs1: 
+      <<: *c_regs
+    rs2: 
+      <<: *c_fregs
+    op_comb: 
+        'rs1 != rs2': 0
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",5,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",5, False,scale_func = lambda x: x*8)': 0
+
+c.fldsp:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*C.*)
+    opcode: 
+      c.fldsp: 0
+    rd: 
+      <<: *all_fregs
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0
+
+c.fsdsp:
+    config: 
+      - check ISA:=regex(.*I.*F.*D.*C.*)
+    opcode: 
+      c.fsdsp: 0
+    rs2: 
+      <<: *all_fregs
+    val_comb:
+        'imm_val > 0': 0
+        'imm_val == 0': 0
+        abstract_comb:
+          'walking_ones("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'walking_zeros("imm_val",6,False, scale_func = lambda x: x*8)': 0
+          'alternate("imm_val",6, False,scale_func = lambda x: x*8)': 0

coverage/dataset.cgf

@@ -180,6 +180,16 @@ datasets:
     x13: 0
     x14: 0
     x15: 0
+
+  c_fregs: &c_fregs
+    f8: 0
+    f9: 0
+    f10: 0
+    f11: 0
+    f12: 0
+    f13: 0
+    f14: 0
+    f15: 0
 
   all_regs_mx2: &all_regs_mx2
     x1: 0

riscv-ctg/riscv_ctg/data/imc.yaml

@@ -1890,3 +1890,178 @@ c.jalr:
     // opcode: c.jalr; op1:$rs1
     TEST_CJALR_OP($testreg, $rs1, $swreg, $offset)
 
+c.flw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs1_op_data: *c_regs 
+  rd_op_data: *c_fregs
+  xlen: [32]
+  std_op:
+  isa: 
+    - IF_Zcf
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  formattype: 'clformat'
+  ea_align_data: '[0,1,2,3]'
+  rs1_val_data: '[0]'
+  imm_val_data: '[x*4 for x in gen_usign_dataset(5)]'
+  template: |-
+    // $comment
+    // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg; fcsr: $fcsr
+    TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg)
+    
+c.flwsp:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rd_op_data: *c_fregs
+  xlen: [32]
+  std_op:
+  isa: 
+    - IF_Zcf
+  formattype: 'ciformat'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: '[x*4 for x in gen_usign_dataset(6)]'  
+  template: |-
+    // $comment
+    // opcode: $inst op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg; fcsr: $fcsr
+    TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg)
+    
+c.fsw:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  xlen: [32]
+  rs1_op_data: *c_regs
+  rs2_op_data: *c_fregs
+  std_op:
+  isa: 
+    - IF_Zcf
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  formattype: 'csformat'
+  ea_align_data: '[0,1,2,3]'
+  rs1_val_data: '[0]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: '[x*4 for x in gen_usign_dataset(5)]'
+  template: |-
+    // $comment
+    /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
+       valreg: $valaddr_reg; valoffset: $val_offset
+    */
+    TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset)
+    
+c.fswsp:
+  sig:
+    stride: 1
+    sz: 'XLEN/8'
+  rs2_op_data: *c_fregs
+  xlen: [32]
+  std_op:
+  isa: 
+    - IF_Zcf
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  formattype: 'cssformat'
+  ea_align_data: '[0,1,2,3]'
+  rs2_val_data: 'gen_sign_dataset(xlen)'
+  imm_val_data: '[x*4 for x in gen_usign_dataset(6)]'
+  template: |-
+    // $comment
+    /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
+       valreg: $valaddr_reg; valoffset: $val_offset
+    */
+    TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset)
+    
+c.fld:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: '8'
+    val_template: "''"
+    load_instr: "fld"
+  rs1_op_data: *c_regs
+  rd_op_data: *c_fregs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IFD_Zcd
+  formattype: 'clformat'
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  ea_align_data: '[0,1,2,3]'
+  imm_val_data: '[x*8 for x in gen_usign_dataset(5)]'
+  template: |-
+    // $comment
+    // opcode: $inst; op1:$rs1; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:$flagreg
+    TEST_LOAD_F($swreg,$testreg,$fcsr,$rs1,$rd,$imm_val,$inst,$ea_align,$flagreg)
+    
+c.fldsp:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  rd_op_data: *c_fregs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IFD_Zcd
+  formattype: 'ciformat'
+  imm_val_data: '[x*8 for x in gen_usign_dataset(6)]'
+  template: |-
+    // $comment
+    // opcode: $inst; op1:x2; dest:$rd; immval:$imm_val; align:$ea_align; flagreg:x4
+    TEST_LOAD_F($swreg,$testreg,$fcsr,x2,$rd,$imm_val,$inst,$ea_align,x4)
+    
+    
+c.fsd:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "''"
+    load_instr: "FLREG"
+  rs1_op_data: *c_regs
+  rs2_op_data: *c_fregs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IFD_Zcd
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  formattype: 'csformat'
+  ea_align_data: '[0,1,2,3]'
+  rs2_val_data: 'gen_sign_dataset(xlen)' 
+  imm_val_data: '[x*8 for x in gen_usign_dataset(5)]'
+  template: |-
+    // $comment
+    /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
+       valreg: $valaddr_reg; valoffset: $val_offset
+    */
+    TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset)
+    
+c.fsdsp:
+  sig:
+    stride: 2
+    sz: 'SIGALIGN'
+  val:
+    stride: 1
+    sz: 'FLEN/8'
+    val_template: "''"
+    load_instr: "FLREG"
+  rs2_op_data: *c_fregs
+  xlen: [32,64]
+  std_op:
+  isa: 
+    - IFD_Zcd
+  fcsr_data: '[x<<5|y for x,y in itertools.product([0,1,2,3,4],range(0,2**5))]'
+  formattype: 'cssformat'
+  ea_align_data: '[0,1,2,3]'
+  rs2_val_data: 'gen_sign_dataset(xlen)' 
+  imm_val_data: '[x*8 for x in gen_usign_dataset(6)]'
+  template: |-
+    // $comment
+    /* opcode: $inst; op1:$rs1; op2:$rs2; op2val:$rs2_val; immval:$imm_val; align:$ea_align; flagreg:$flagreg;
+     valreg: $valaddr_reg; valoffset: $val_offset
+    */
+    TEST_STORE_F($swreg,$testreg,$fcsr,$rs1,$rs2,$imm_val,$offset,$inst,$ea_align,$flagreg,$valaddr_reg, $val_offset)