replaced lw/sw with ld/sd for pmp64 tests

riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-R-priority-level-2.S

@@ -39,16 +39,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-R-priority.S

@@ -41,16 +41,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-R.S

@@ -43,16 +43,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RW-priority-level-2.S

@@ -39,16 +39,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RW-priority.S

@@ -40,16 +40,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RW.S

@@ -45,16 +45,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RWX.S

@@ -43,16 +43,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RX-priority-level-2.S

@@ -39,16 +39,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RX-priority.S

@@ -40,16 +40,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-RX.S

@@ -43,16 +43,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-X-priority-level-2.S

@@ -39,16 +39,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-X-priority.S

@@ -40,16 +40,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NA4-X.S

@@ -43,16 +43,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-R-priority-level-2.S

@@ -39,16 +39,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-R-priority.S

@@ -40,16 +40,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-R.S

@@ -44,16 +44,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RW-priority-level-2.S

@@ -39,16 +39,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RW-priority.S

@@ -40,16 +40,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RW.S

@@ -44,16 +44,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm
 

riscv-test-suite/rv64i_m/pmp64/pmp64-NAPOT-RWX.S

@@ -44,16 +44,16 @@ RVTEST_SIGBASE( x13,signature_x13_1)
 #define NOP 		0x13
 .macro VERIFICATION_RWX		ADDRESS	
    	LA(a5, \ADDRESS)	// Fetch the address to be checked
-    	lw	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
+    	ld	a4,0(a5)	// Load data from it (CHECK FOR READ) ; (NOT TRAP => W enabled)
     	nop
     	nop
     	/* WRITING new value to memory region
     	TRAP if the WRITability is blocked */
 	LI(a4, 	NOP)		// Load the new value (NOP Instruction ID) 
-	sw	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
+	sd	a4,0(a5)	// Store the new value (NOT TRAP => W enabled)
 	nop
 	nop
-	lw	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
+	ld	a4,0(a5)	// Reload for verification (CHECK IF DATA HAS BEEN UPDATED SUCCESSFULLY)
 	jal	\ADDRESS	// Test for execution, an instruction is placed at this address 
 .endm