fixed 64bit write mucounteren csr error

riscv-mcu · Aug 17, 2022 · d988524 · d988524
1 parent bc99e84
commit d988524
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
@@ -1261,6 +1261,7 @@ static int write_mucounteren(CPURISCVState *env, int csrno, target_ulong val)
 {
     extern int use_icount;
     extern int icount_shift_flag;
+    val = val & 0xffffffff;
     if(first_run_flag == 0)
     {
         if(use_icount)