target/riscv: update some macro

1. update RISCV_MAX_HARTS to 2^20 according to SPEC 2. remove RISCV_MAX_REGISTERS, it's not used anywhere anymore 3. add parentheses Change-Id: Iadf0fa1ba3bbe5b9420b8430883e140db87f4f9e Signed-off-by: Mark Zhuang <[email protected]>
riscv-collab · Jul 13, 2023 · 04d8cfc · 04d8cfc
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diff --git a/doc/openocd.texi b/doc/openocd.texi
@@ -10596,11 +10596,9 @@ addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
 @section RISC-V Architecture
 
 @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
-debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
-harts. (It's possible to increase this limit to 1024 by changing
-RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
-Debug Specification, but there is also support for legacy targets that
-implement version 0.11.
+debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 2^20
+harts. OpenOCD primarily supports 0.13 of the RISC-V Debug Specification,
+but there is also support for legacy targets that implement version 0.11.
 
 @subsection RISC-V Terminology
 

diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h
@@ -12,12 +12,11 @@ struct riscv_program;
 #include "target/register.h"
 #include "target/semihosting_common.h"
 #include <helper/command.h>
+#include <helper/bits.h>
 
 #define RISCV_COMMON_MAGIC	0x52495356U
 
-/* The register cache is statically allocated. */
-#define RISCV_MAX_HARTS 1024
-#define RISCV_MAX_REGISTERS 5000
+#define RISCV_MAX_HARTS  ((int)BIT(20))
 #define RISCV_MAX_TRIGGERS 32
 #define RISCV_MAX_HWBPS 16
 
@@ -30,7 +29,7 @@ struct riscv_program;
 #define RISCV_HGATP_PPN(xlen)  ((xlen) == 32 ? HGATP32_PPN : HGATP64_PPN)
 #define RISCV_PGSHIFT 12
 
-# define PG_MAX_LEVEL 4
+#define PG_MAX_LEVEL 4
 
 #define RISCV_NUM_MEM_ACCESS_METHODS  3