[LLVM][XTHeadVector] Implement intrinsics for vwadd/vwsub. (llvm#51)

* [LLVM][XTHeadVector] Define intrinsic function for vwadd/vwsub, etc.

* [LLVM][XTHeadVector] Redefine MxList and AllWidenableVectors for xtheadvector.

* [LLVM][XTHeadVector] Define pseudos for vwadd, etc.

* [LLVM][XTHeadVector] Define TiedBinary Pseudos.
This is in reference of https://reviews.llvm.org/D103211 and https://reviews.llvm.org/D103552.

* [LLVM][XTHeadVector] Define patterns and map intrinsics to pseudos.
The defination and usage of TiedBinary Pat reference https://reviews.llvm.org/D103211 and https://reviews.llvm.org/D103552 as well.

* [LLVM][XTHeadVector] Update the convertToThreeAddress method, to convert xtheadvector pseudos.

* [LLVM][XTHeadVector] Add test cases for vwadd{u}/vwsub{u}.

* [LLVM][XTHeadVector] Add test cases for vwadd{u}.{wv/wx}/vwsub{u}.{wv/wx}.

* [NFC][XTHeadVector] Update README.

README.md

@@ -27,6 +27,10 @@ Any feature not listed below but present in the specification should be consider
       - (Done) `vadd.{vv,vx,vi}`
       - (Done) `vsub.{vv,vx}`
       - (Done) `vrsub.{vx,vi}`
+    - (Done) `12.2. Vector Widening Integer Add/Subtract`
+      - (Done) `vwadd{u}.{vv,vx,wv,wx}`
+      - (Done) `vwsub{u}.{vv,vx,wv,wx}`
+
 - (WIP) Clang intrinsics related to the `XTHeadVector` extension:
   - (WIP) `6. Configuration-Setting and Utility`
     - (Done) `6.1. Set vl and vtype`

llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td

@@ -574,10 +574,27 @@ let TargetPrefix = "riscv" in {
     let VLOperand = 4;
   }
 
+  // For destination vector type is NOT the same as
+  // first source vector (with mask but no policy).
+  // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vl)
+  class XVBinaryABXMasked
+        : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty,
+                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
+                    [IntrNoMem]>, RISCVVIntrinsic {
+    let ScalarOperand = 2;
+    let VLOperand = 4;
+  }
+
   multiclass XVBinaryAAX {
     def "int_riscv_" # NAME : RISCVBinaryAAXUnMasked;
     def "int_riscv_" # NAME # "_mask" : XVBinaryAAXMasked;
   }
+
+  multiclass XVBinaryABX {
+    def "int_riscv_" # NAME : RISCVBinaryABXUnMasked;
+    def "int_riscv_" # NAME # "_mask" : XVBinaryABXMasked;
+  }
 }
 
 let TargetPrefix = "riscv" in {
@@ -586,6 +603,16 @@ let TargetPrefix = "riscv" in {
   defm th_vadd : XVBinaryAAX;
   defm th_vsub : XVBinaryAAX;
   defm th_vrsub : XVBinaryAAX;
+
+  // 12.2. Vector Widening Integer Add/Subtract
+  defm th_vwaddu : XVBinaryABX;
+  defm th_vwadd : XVBinaryABX;
+  defm th_vwaddu_w : XVBinaryAAX;
+  defm th_vwadd_w : XVBinaryAAX;
+  defm th_vwsubu : XVBinaryABX;
+  defm th_vwsub : XVBinaryABX;
+  defm th_vwsubu_w : XVBinaryAAX;
+  defm th_vwsub_w : XVBinaryAAX;
 } // TargetPrefix = "riscv"
 
 let TargetPrefix = "riscv" in {

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

@@ -2577,6 +2577,9 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
 #define CASE_WIDEOP_OPCODE_COMMON(OP, LMUL)                                    \
   RISCV::PseudoV##OP##_##LMUL##_TIED
 
+#define CASE_TH_WIDEOP_OPCODE_COMMON(OP, LMUL)                                 \
+  RISCV::PseudoTH_V##OP##_##LMUL##_TIED
+
 #define CASE_WIDEOP_OPCODE_LMULS_MF4(OP)                                       \
   CASE_WIDEOP_OPCODE_COMMON(OP, MF4):                                          \
   case CASE_WIDEOP_OPCODE_COMMON(OP, MF2):                                     \
@@ -2587,13 +2590,23 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
 #define CASE_WIDEOP_OPCODE_LMULS(OP)                                           \
   CASE_WIDEOP_OPCODE_COMMON(OP, MF8):                                          \
   case CASE_WIDEOP_OPCODE_LMULS_MF4(OP)
+
+#define CASE_TH_WIDEOP_OPCODE_LMULS(OP)                                        \
+  CASE_TH_WIDEOP_OPCODE_COMMON(OP, M1):                                        \
+  case CASE_TH_WIDEOP_OPCODE_COMMON(OP, M2):                                   \
+  case CASE_TH_WIDEOP_OPCODE_COMMON(OP, M4)
 // clang-format on
 
 #define CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL)                             \
   case RISCV::PseudoV##OP##_##LMUL##_TIED:                                     \
     NewOpc = RISCV::PseudoV##OP##_##LMUL;                                      \
     break;
 
+#define CASE_TH_WIDEOP_CHANGE_OPCODE_COMMON(OP, LMUL)                          \
+  case RISCV::PseudoTH_V##OP##_##LMUL##_TIED:                                  \
+    NewOpc = RISCV::PseudoTH_V##OP##_##LMUL;                                   \
+    break;
+
 #define CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP)                                 \
   CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF4)                                    \
   CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF2)                                    \
@@ -2605,6 +2618,11 @@ MachineInstr *RISCVInstrInfo::commuteInstructionImpl(MachineInstr &MI,
   CASE_WIDEOP_CHANGE_OPCODE_COMMON(OP, MF8)                                    \
   CASE_WIDEOP_CHANGE_OPCODE_LMULS_MF4(OP)
 
+#define CASE_TH_WIDEOP_CHANGE_OPCODE_LMULS(OP)                                 \
+  CASE_TH_WIDEOP_CHANGE_OPCODE_COMMON(OP, M1)                                  \
+  CASE_TH_WIDEOP_CHANGE_OPCODE_COMMON(OP, M2)                                  \
+  CASE_TH_WIDEOP_CHANGE_OPCODE_COMMON(OP, M4)
+
 MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI,
                                                     LiveVariables *LV,
                                                     LiveIntervals *LIS) const {
@@ -2646,12 +2664,20 @@ MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI,
   case CASE_WIDEOP_OPCODE_LMULS(WADD_WV):
   case CASE_WIDEOP_OPCODE_LMULS(WADDU_WV):
   case CASE_WIDEOP_OPCODE_LMULS(WSUB_WV):
-  case CASE_WIDEOP_OPCODE_LMULS(WSUBU_WV): {
+  case CASE_WIDEOP_OPCODE_LMULS(WSUBU_WV):
+  case CASE_TH_WIDEOP_OPCODE_LMULS(WADD_WV):
+  case CASE_TH_WIDEOP_OPCODE_LMULS(WADDU_WV):
+  case CASE_TH_WIDEOP_OPCODE_LMULS(WSUB_WV):
+  case CASE_TH_WIDEOP_OPCODE_LMULS(WSUBU_WV): {
     // If the tail policy is undisturbed we can't convert.
-    assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags) &&
-           MI.getNumExplicitOperands() == 6);
-    if ((MI.getOperand(5).getImm() & 1) == 0)
-      return nullptr;
+    // We can always do the conversion in RVV 0.7.1, since
+    // it is always tail agnostic.
+    if (!STI.hasVendorXTHeadV()) {
+      assert(RISCVII::hasVecPolicyOp(MI.getDesc().TSFlags) &&
+            MI.getNumExplicitOperands() == 6);
+      if ((MI.getOperand(5).getImm() & 1) == 0)
+        return nullptr;
+    }
 
     // clang-format off
     unsigned NewOpc;
@@ -2662,6 +2688,10 @@ MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI,
     CASE_WIDEOP_CHANGE_OPCODE_LMULS(WADDU_WV)
     CASE_WIDEOP_CHANGE_OPCODE_LMULS(WSUB_WV)
     CASE_WIDEOP_CHANGE_OPCODE_LMULS(WSUBU_WV)
+    CASE_TH_WIDEOP_CHANGE_OPCODE_LMULS(WADD_WV)
+    CASE_TH_WIDEOP_CHANGE_OPCODE_LMULS(WADDU_WV)
+    CASE_TH_WIDEOP_CHANGE_OPCODE_LMULS(WSUB_WV)
+    CASE_TH_WIDEOP_CHANGE_OPCODE_LMULS(WSUBU_WV)
     }
     // clang-format on
 
@@ -2672,8 +2702,9 @@ MachineInstr *RISCVInstrInfo::convertToThreeAddress(MachineInstr &MI,
               .add(MI.getOperand(1))
               .add(MI.getOperand(2))
               .add(MI.getOperand(3))
-              .add(MI.getOperand(4))
-              .add(MI.getOperand(5));
+              .add(MI.getOperand(4));
+    if (!STI.hasVendorXTHeadV())
+      MIB.add(MI.getOperand(5));
   }
   }
   MIB.copyImplicitOps(MI);