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Fixes bug in verilog name generation logic #1016

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Fixes #941

@rdaly525 rdaly525 requested review from leonardt and joyliu37 July 22, 2021 03:09
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Looks good to me. So I need to use serializeToFile to dump the generator information?

->getMetaData()["verilog"];
module_name = make_name(instance_module->getName(), verilog_json);
}
if (instance_module->isGenerated() && instance_module->getGenerator()->getMetaData().count("verilog") > 0) {
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@joyliu37 joyliu37 Jul 22, 2021

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After testing with clockwork, I need to change this line of code into

if (instance_module->isGenerated() && instance_module->getMetaData().count("verilog") > 0)

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@rdaly525 I think this means you need to check two separate cases here:

  1. the instance_module has "verilog" metadata
  2. the instance_module->getGenerator() has "verilog" metadata

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Change looks fine, but I think there's one extra case needed for Joey's use case

->getMetaData()["verilog"];
module_name = make_name(instance_module->getName(), verilog_json);
}
if (instance_module->isGenerated() && instance_module->getGenerator()->getMetaData().count("verilog") > 0) {
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@rdaly525 I think this means you need to check two separate cases here:

  1. the instance_module has "verilog" metadata
  2. the instance_module->getGenerator() has "verilog" metadata

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Add a Custom Name for CoreIR Generator When Generate Verilog
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