armstub7: Various fixes #85
Conversation
The previous code was enabling both I and D-caches, but keeping the bit M as the reset value, which is architecturally undetermined. In practice, in both Cortex-A7 and Cortex-A53, the reset value is 0, so the D-cache was disabled (but the I-cache was enabled). For the 32-bit Arm architecture boot, the Linux kernel expects the data cache and MMU to be disabled when the CPU jumps into it, the I-cache doesn't matter, as specified in the file `Documentation/arm/Booting` of the Linux kernel tree under `Calling the kernel image`. This patch disables the D-cache and MMU for correctness while keeping the I-cache enabled to save a few cycles during the execution of the stub. Signed-off-by: Antonio Niño Díaz <[email protected]>
|
For other reviewers, see http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0438i/BABJAHDA.html for details of the System Control Register. |
|
While it is true that for A7 and A53 both C and M bits are set to 0 on reset (according to their technical reference manuals), the ARM ARM says (at least, the ARMv8 ARM) |
|
Relevant links: ARMv8 ARM (no online version, just pdf): https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile |
According to the Technical Reference Manuals of both Cortex-A7 and Cortex-A53, SMP must be enabled before enabling any caches. Signed-off-by: Antonio Niño Díaz <[email protected]>
In Cortex-A7, some reserved fields of NSACR were set to 1. According to the Technical Reference Manual, the reserved fields of this register are RAZ/WI (Read-As-Zero, Writes Ignored). In Cortex-A53, all reserved fields are RES0. Software should respect this for future compatibility. The bits NS_SMP and NS_L2ERR of Cortex-A7 need to be set to 1 in order for the Non-secure world to be able to modify the value of the SMP and L2 AXI asynchronous error bits. However, in Cortex-A53 they are RES0. This means that both CPUs can't share the same reset value. Signed-off-by: Antonio Niño Díaz <[email protected]>
This register can be accessed from both user and privileged modes and it is not used in the bootstrap, there is no reason to initialize it here. Signed-off-by: Antonio Niño Díaz <[email protected]>
AntonioND
changed the title
|
I've added a couple of commits to fix other issues with this bootstrap ( I'm not sure about Note that I don't have a Raspberry Pi 2 to test the Cortex-A7 code. |
|
The changes look quite reasonable. Will need double checking on Pi2/Pi3 and force_core firmware code may need patching, but otherwise seems fine. |
|
@popcornmix Is there someone at the Raspberry Pi Foundation that can double check the pi2/pi3? It would be nice to get the PR landed. Many thanks. |
- The bootstub has been completely rewritten taking advantage of the Thumb-2 instruction set, which results in major space gains - Res0 bits of NSACR are no longer set (supersedes #85) - CNTVOFF is set to zero, now consistent with armstub8 (supersedes #113) - SMC instructions are now disabled, now consistent with armstub8 - ACTLR is now configured to allow Non-secure access to several CPU configuration registers (CPUACTLR/CPUECTLR/L2CTLR/L2ECTLR/L2ACTLR), which makes it possible to e.g. enable Spectre v4 mitigations directly in the kernel without needing a separate bootstub variant (potentially supersedes #115) Free space in each affected bootstub after this commit: armstub7.bin: 108 bytes armstub8-32.bin: 104 bytes armstub8-32-gic.bin: 44 bytes (!)
Various fixes to armstub7.
Original message:
Fixes #84