clk: bcm2835: Don't rate change PLLs on behalf of dividers.

Our core PLLs are intended to be configured once and left alone. With the flag set, asking to set the PLLD_DSI1 clock rate would change PLLD just to get closer to the requested DSI clock, thus changing PLLD_PER, the UART and ethernet PHY clock rates downstream of it, and breaking ethernet. Signed-off-by: Eric Anholt <[email protected]>
raspberrypi · Aug 9, 2016 · 2b8dfa3 · 2b8dfa3
1 parent 3ac11dc
commit 2b8dfa3
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
@@ -1209,7 +1209,7 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
 	init.num_parents = 1;
 	init.name = divider_name;
 	init.ops = &bcm2835_pll_divider_clk_ops;
-	init.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED;
+	init.flags = CLK_IGNORE_UNUSED;
 
 	divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
 	if (!divider)