Fixing panics in release mode #72
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500 µs is really worrying long given the 2 µs that TI mentions.
https://e2e.ti.com/support/data-converters/f/73/t/755048
This is certainly ok for now (i.e. it doesn't hurt). But I suspect that something else is wrong.
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Note that the link you're referring to is discussing the hardware reset pin, but we're dealing with the software reset here. It's very possible that the software reset is more complicated than the hardware reset circuit. I'm posting on the TI forums to see if I can get any information about timing requirements - I'm not a fan of this being unspecified and it can result in hard-to-diagnose bugs in the field if it doesn't work right. |
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Sure. But for the device with the "similar reset circuitry" (as per the TI link), they cover software and hardware resets with the same specs in terms of dead time.
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But I'm happy to leave it at 500 µs now and your trace clearly shows that it NAK'ed after 100 µs. |
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I'm going to merge this as-is, but there's an open TI request here: https://e2e.ti.com/support/data-converters/f/73/t/945550 - I'd really like to get some more information from them, as this could be a really annoying bug in the field. |
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Further investigations are tracked in #77 |
This PR fixes #67 by increasing the delay after the software reset of the ADS7924 (power monitor external ADC) from 100uS to 500uS. It was found that 100uS was not always sufficient for the reset to occur.