Transpiler refactor

[csookim]

This covers issue #1493.

This PR updates the qubit representation in qibo to support hardware execution after transpilation. Circuit.wire_names and Gate.qubits will be used on the hardware side.

Terms

• physical qubit = qubit name = Circuit.wire_names: list[str | int]
• logical qubit = qubit index = Gate.qubits: Tuple[int, ...]
• connectivity = nx.Graph
• mapping = qubit layout

Updates

• Removed initial_layout, which was used to represent the mapping between {physical qubit: logical qubit}.
• wire_names itself serves as the mapping. Qubit i corresponds to the physical qubit named wire_names[i].

Transpiler

• To transpile a circuit, the user must provide connectivity representing the hardware.
• Node names in connectivity must match the wire_names in the circuit.
• Placer calculates the placement based on connectivity and circuit. It updates the wire_names directly with no return value.
• Router does routing based on connectivity and circuit, returning a new_circuit and final_mapping.

Checklist:

• Reviewers confirm new code works as expected.
• Tests are passing.
• Coverage does not decrease.
• Documentation is updated.

[codecov]

Codecov Report

All modified and coverable lines are covered by tests ✅

Project coverage is 99.71%. Comparing base (faa5a7c) to head (049ff01).
Report is 40 commits behind head on master.

Additional details and impacted files

@@            Coverage Diff             @@
##           master    #1500      +/-   ##
==========================================
- Coverage   99.72%   99.71%   -0.01%     
==========================================
  Files          80       81       +1     
  Lines       11783    11737      -46     
==========================================
- Hits        11751    11704      -47     
- Misses         32       33       +1     

Flag	Coverage Δ
unittests	99.71% <100.00%> (-0.01%)	⬇️

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