v1.19.0

Added

• stream_to_mem: Allows to use memories with flow control (req/gnt) for requests but
  without flow control for output data to be used in streams.
• isochronous_spill_register: Isochronous clock domain crossing cutting all paths.
• rr_arb_tree_tb: Systemverilog testbench for rr_arb_tree, which checks for fair throughput.
• cf_math_pkg::idx_width: Constant function for defining the binary representation width
  of an index signal.

Changed

• addr_decode: Use cf_math_pkg::idx_width for computing the index width, inline documentation.
• lzc: Use cf_math_pkg::idx_width for computing the index width, inline documentation.
• Bender: Change levels of modules affected by depending on cf_math_pkg::idx_width().
• stream_xbar: Fully connected stream bassed interconnect with variable number of inputs and outputs.
• stream_xbar: Fully connected stream-bassed interconnect with a variable number of inputs and outputs.

Fixed

• Improve tool compatibility.
• rr_arb_tree: Properly degenerate rr_i and idx_o signals.
• rr_arb_tree: Add parameter FairArb to distribute throughput of input requests evenly when
  not all inputs have requests active.
• stream_demux: Properly degenerate inp_sel_i signal.