hw: Connect number of LLC accesses info to cheshire regs
reviewdog [verible-verilog-lint] report
reported by reviewdog 🐶
Findings (4)
hw/cheshire_soc.sv|454 col 101| Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]
hw/cheshire_soc.sv|569 col 101| Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
hw/cheshire_soc.sv|572 col 101| Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
hw/cheshire_soc.sv|573 col 101| Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
Filtered Findings (0)
Annotations
Check warning on line 454 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L454
Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 103 [Style: line-length] [line-length]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:454 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 569 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L569
Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:569 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 572 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L572
Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:572 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 573 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L573
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:573 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}