Skip to content

Commit

Permalink
hw: bump to pulp-v2 parametrization
Browse files Browse the repository at this point in the history
  • Loading branch information
@mp-17
mp-17 committed Jan 12, 2025
1 parent de21a1f commit d77d147
Show file tree
Hide file tree
Showing 2 changed files with 101 additions and 106 deletions.
97 changes: 33 additions & 64 deletions hw/cheshire_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -486,74 +486,43 @@ package cheshire_pkg;
endcase
endfunction

function automatic config_pkg::cva6_cfg_t gen_cva6_cfg(cheshire_cfg_t cfg);
function automatic config_pkg::cva6_user_cfg_t gen_cva6_cfg(cheshire_cfg_t cfg);
doub_bt SizeSpm = get_llc_size(cfg);
doub_bt SizeLlcOut = cfg.LlcOutRegionEnd - cfg.LlcOutRegionStart;
doub_bt CieBase = cfg.Cva6ExtCieOnTop ? 64'h8000_0000 - cfg.Cva6ExtCieLength : 64'h2000_0000;
doub_bt NoCieBase = cfg.Cva6ExtCieOnTop ? 64'h2000_0000 : 64'h2000_0000 + cfg.Cva6ExtCieLength;
return config_pkg::cva6_cfg_t'{
NrCommitPorts : 2,
AxiAddrWidth : cfg.AddrWidth,
AxiDataWidth : cfg.AxiDataWidth,
AxiIdWidth : Cva6IdWidth,
AxiUserWidth : cfg.AxiUserWidth,
NrLoadBufEntries : 2,
FpuEn : 1,
XF16 : 0,
XF16ALT : 0,
XF8 : 0,
XF8ALT : 0,
RVA : 1,
RVB : 0,
RVV : cfg.Ara,
RVC : 1,
RVH : ~cfg.Ara,
RVZCB : 1,
XFVec : 0,
CvxifEn : 0,
ZiCondExtEn : 1,
RVSCLIC : cfg.Clic,
RVF : 1,
RVD : 1,
FpPresent : 1,
NSX : 0,
FLen : 64,
RVFVec : 0,
XF16Vec : 0,
XF16ALTVec : 0,
XF8Vec : 0,
NrRgprPorts : 0,
NrWbPorts : 0,
EnableAccelerator : 0,
RVS : 1,
RVU : 1,
HaltAddress : AmDbg + 'h800,
ExceptionAddress : AmDbg + 'h808,
RASDepth : cfg.Cva6RASDepth,
BTBEntries : cfg.Cva6BTBEntries,
BHTEntries : cfg.Cva6BHTEntries,
DmBaseAddress : AmDbg,
TvalEn : 1,
NrPMPEntries : cfg.Cva6NrPMPEntries,
PMPCfgRstVal : {16{64'h0}},
PMPAddrRstVal : {16{64'h0}},
PMPEntryReadOnly : 16'd0,
NOCType : config_pkg::NOC_TYPE_AXI4_ATOP,
CLICNumInterruptSrc : NumCoreIrqs + NumIntIntrs + cfg.NumExtClicIntrs,
NrNonIdempotentRules : 2, // Periphs, ExtNonCIE
NonIdempotentAddrBase : {64'h0000_0000, NoCieBase},
NonIdempotentLength : {64'h1000_0000, 64'h6000_0000 - cfg.Cva6ExtCieLength},
NrExecuteRegionRules : 5, // Debug, Bootrom, AllSPM, LLCOut, ExtCIE
ExecuteRegionAddrBase : {AmDbg, AmBrom, AmSpm, cfg.LlcOutRegionStart, CieBase},
ExecuteRegionLength : {64'h40000, 64'h40000, 2*SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength},
NrCachedRegionRules : 3, // CachedSPM, LLCOut, ExtCIE
CachedRegionAddrBase : {AmSpm, cfg.LlcOutRegionStart, CieBase},
CachedRegionLength : {SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength},
MaxOutstandingStores : 7,
DebugEn : 1,
NonIdemPotenceEn : 0,
AxiBurstWriteEn : 0
};
// Base our config on the upstream default for this variant
config_pkg::cva6_user_cfg_t ret = cva6_config_pkg::cva6_cfg;
// Modify what we need to
ret.AxiAddrWidth = cfg.AddrWidth;
ret.AxiDataWidth = cfg.AxiDataWidth;
ret.AxiIdWidth = Cva6IdWidth;
ret.AxiUserWidth = cfg.AxiUserWidth;
ret.DmBaseAddress = AmDbg;
ret.HaltAddress = AmDbg + 'h800;
ret.ExceptionAddress = AmDbg + 'h808;
ret.NrNonIdempotentRules = 2; // Periphs, ExtNonCI;
ret.NonIdempotentAddrBase = {64'h0000_0000, NoCieBase};
ret.NOCType = config_pkg::NOC_TYPE_AXI4_ATOP;
ret.NonIdempotentLength = {64'h1000_0000, 64'h6000_0000 - cfg.Cva6ExtCieLength};
ret.NrExecuteRegionRules = 5; // Debug, Bootrom, AllSPM, LLCOut, ExtCI;
ret.ExecuteRegionAddrBase = {AmDbg, AmBrom, AmSpm, cfg.LlcOutRegionStart, CieBase};
ret.ExecuteRegionLength = {64'h40000, 64'h40000, 2*SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength};
ret.NrCachedRegionRules = 3; // CachedSPM, LLCOut, ExtCI;
ret.CachedRegionAddrBase = {AmSpm, cfg.LlcOutRegionStart, CieBase};
ret.CachedRegionLength = {SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength};
ret.DebugEn = 1;
// ret.RVSCLIC = cfg.Clic;
// ret.CLICNumInterruptSrc = NumCoreIrqs + NumIntIntrs + cfg.NumExtClicIntrs;
// TODO: Should some things be removed from the main config?
// TODO: Should other things be added to the main config?
// TODO: Tune missing parameters of interest (esp. cache and interconnect) properly
ret.RASDepth = cfg.Cva6RASDepth;
ret.BTBEntries = cfg.Cva6BTBEntries;
ret.BHTEntries = cfg.Cva6BHTEntries;
ret.NrPMPEntries = cfg.Cva6NrPMPEntries;
// Return modified config
return ret;
endfunction

////////////////
Expand Down
110 changes: 68 additions & 42 deletions hw/cheshire_soc.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -112,6 +112,7 @@ module cheshire_soc import cheshire_pkg::*; #(
`include "common_cells/registers.svh"
`include "common_cells/assertions.svh"
`include "cheshire/typedef.svh"
`include "ara/intf_typedef.svh"

// Declare interface types internally
`CHESHIRE_TYPEDEF_ALL(, Cfg)
Expand Down Expand Up @@ -554,31 +555,10 @@ module cheshire_soc import cheshire_pkg::*; #(
// Cores //
/////////////

// TODO: Implement X interface support

// Accelerator ports
acc_pkg::cva6_to_acc_t acc_req;
acc_pkg::acc_to_cva6_t acc_resp;

// CVA6-Ara memory consistency
logic acc_cons_en;
logic [Cfg.AddrWidth-1:0] inval_addr;
logic inval_valid;
logic inval_ready;

// Pack invalidation interface into acc interface
acc_pkg::acc_to_cva6_t acc_resp_pack;
always_comb begin : pack_inval
acc_resp_pack = acc_resp;
acc_resp_pack.acc_resp.inval_valid = inval_valid;
acc_resp_pack.acc_resp.inval_addr = inval_addr;
inval_ready = acc_req.acc_req.inval_ready;
acc_cons_en = acc_req.acc_req.acc_cons_en;
end

`CHESHIRE_TYPEDEF_AXI_CT(axi_cva6, addr_t, cva6_id_t, axi_data_t, axi_strb_t, axi_user_t)

localparam config_pkg::cva6_cfg_t Cva6Cfg = gen_cva6_cfg(Cfg);
localparam config_pkg::cva6_user_cfg_t Cva6UsrCfg = gen_cva6_cfg(Cfg);
localparam config_pkg::cva6_cfg_t Cva6Cfg = build_config_pkg::build_config(Cva6UsrCfg);

// Boot from boot ROM only if available, otherwise from platform ROM
localparam logic [63:0] BootAddr = 64'(Cfg.Bootrom ? AmBrom : Cfg.PlatformRom);
Expand Down Expand Up @@ -607,6 +587,39 @@ module cheshire_soc import cheshire_pkg::*; #(

assign intr.intn.bus_err.cores = core_bus_err_intr_comb;

// TODO: Implement X interface support
// Define the exception type
`CVA6_TYPEDEF_EXCEPTION(exception_t, Cva6Cfg);
// Standard interface
`CVA6_INTF_TYPEDEF_ACC_REQ(accelerator_req_t, Cva6Cfg, fpnew_pkg::roundmode_e);
`CVA6_INTF_TYPEDEF_ACC_RESP(accelerator_resp_t, Cva6Cfg, exception_t);
// MMU interface
`CVA6_INTF_TYPEDEF_MMU_REQ(acc_mmu_req_t, Cva6Cfg);
`CVA6_INTF_TYPEDEF_MMU_RESP(acc_mmu_resp_t, Cva6Cfg, exception_t);
// Accelerator - CVA6's top-level interface
`CVA6_INTF_TYPEDEF_CVA6_TO_ACC(cva6_to_acc_t, accelerator_req_t, acc_mmu_resp_t);
`CVA6_INTF_TYPEDEF_ACC_TO_CVA6(acc_to_cva6_t, accelerator_resp_t, acc_mmu_req_t);

// Accelerator ports
cva6_to_acc_t acc_req;
acc_to_cva6_t acc_resp;

// CVA6-Ara memory consistency
logic acc_cons_en;
logic [Cfg.AddrWidth-1:0] inval_addr;
logic inval_valid;
logic inval_ready;

// Pack invalidation interface into acc interface
acc_to_cva6_t acc_resp_pack;
always_comb begin : pack_inval
acc_resp_pack = acc_resp;
acc_resp_pack.acc_resp.inval_valid = inval_valid;
acc_resp_pack.acc_resp.inval_addr = inval_addr;
inval_ready = acc_req.acc_req.inval_ready;
acc_cons_en = acc_req.acc_req.acc_cons_en;
end

for (genvar i = 0; i < NumIntHarts; i++) begin : gen_cva6_cores
axi_cva6_req_t core_out_req, core_ur_req;
axi_cva6_rsp_t core_out_rsp, core_ur_rsp;
Expand All @@ -620,16 +633,20 @@ module cheshire_soc import cheshire_pkg::*; #(
riscv::priv_lvl_t clic_irq_priv;

cva6 #(
.CVA6Cfg ( Cva6Cfg ),
.axi_ar_chan_t ( axi_cva6_ar_chan_t ),
.axi_aw_chan_t ( axi_cva6_aw_chan_t ),
.axi_w_chan_t ( axi_cva6_w_chan_t ),
.b_chan_t ( axi_cva6_b_chan_t ),
.r_chan_t ( axi_cva6_r_chan_t ),
.cvxif_req_t ( acc_pkg::cva6_to_acc_t ),
.cvxif_resp_t ( acc_pkg::acc_to_cva6_t ),
.noc_req_t ( axi_cva6_req_t ),
.noc_resp_t ( axi_cva6_rsp_t )
.CVA6Cfg ( Cva6Cfg ),
.axi_ar_chan_t ( axi_cva6_ar_chan_t ),
.axi_aw_chan_t ( axi_cva6_aw_chan_t ),
.axi_w_chan_t ( axi_cva6_w_chan_t ),
.b_chan_t ( axi_cva6_b_chan_t ),
.r_chan_t ( axi_cva6_r_chan_t ),
.cvxif_req_t ( cva6_to_acc_t ),
.cvxif_resp_t ( acc_to_cva6_t ),
.noc_req_t ( axi_cva6_req_t ),
.noc_resp_t ( axi_cva6_rsp_t ),
.accelerator_req_t ( accelerator_req_t ),
.accelerator_resp_t ( accelerator_resp_t ),
.acc_mmu_req_t ( acc_mmu_req_t ),
.acc_mmu_resp_t ( acc_mmu_resp_t )
) i_core_cva6 (
.clk_i,
.rst_ni,
Expand All @@ -639,14 +656,14 @@ module cheshire_soc import cheshire_pkg::*; #(
.ipi_i ( msip[i] ),
.time_irq_i ( mtip[i] ),
.debug_req_i ( dbg_int_req[i] ),
.clic_irq_valid_i ( clic_irq_valid ),
.clic_irq_id_i ( clic_irq_id ),
.clic_irq_level_i ( clic_irq_level ),
.clic_irq_priv_i ( clic_irq_priv ),
.clic_irq_shv_i ( clic_irq_shv ),
.clic_irq_ready_o ( clic_irq_ready ),
.clic_kill_req_i ( clic_irq_kill_req ),
.clic_kill_ack_o ( clic_irq_kill_ack ),
// .clic_irq_valid_i ( clic_irq_valid ),
// .clic_irq_id_i ( clic_irq_id ),
// .clic_irq_level_i ( clic_irq_level ),
// .clic_irq_priv_i ( clic_irq_priv ),
// .clic_irq_shv_i ( clic_irq_shv ),
// .clic_irq_ready_o ( clic_irq_ready ),
// .clic_kill_req_i ( clic_irq_kill_req ),
// .clic_kill_ack_o ( clic_irq_kill_ack ),
.rvfi_probes_o ( ),
.cvxif_req_o ( acc_req ),
.cvxif_resp_i ( acc_resp_pack ),
Expand Down Expand Up @@ -789,6 +806,15 @@ module cheshire_soc import cheshire_pkg::*; #(
ara #(
.NrLanes ( Cfg.AraNrLanes ),
.VLEN ( Cfg.AraVLEN ),
.OSSupport ( 1'b1 ),
.CVA6Cfg ( Cva6Cfg ),
.exception_t ( exception_t ),
.accelerator_req_t (accelerator_req_t ),
.accelerator_resp_t(accelerator_resp_t),
.acc_mmu_req_t (acc_mmu_req_t ),
.acc_mmu_resp_t (acc_mmu_resp_t ),
.cva6_to_acc_t (cva6_to_acc_t ),
.acc_to_cva6_t (acc_to_cva6_t ),
.AxiDataWidth ( AraDataWideWidth ),
.AxiAddrWidth ( Cfg.AddrWidth ),
.axi_ar_t ( axi_ara_wide_ar_chan_t ),
Expand All @@ -814,7 +840,7 @@ module cheshire_soc import cheshire_pkg::*; #(
axi_inval_filter #(
.MaxTxns ( 4 ),
.AddrWidth ( Cfg.AddrWidth ),
.L1LineWidth( ariane_pkg::DCACHE_LINE_WIDTH/8 ),
.L1LineWidth( Cva6Cfg.DCACHE_LINE_WIDTH/8 ),
.aw_chan_t ( axi_ara_wide_aw_chan_t ),
.req_t ( axi_ara_wide_req_t ),
.resp_t ( axi_ara_wide_resp_t )
Expand Down

0 comments on commit d77d147

Please sign in to comment.