fpga: Start working on SPI driver

pulp-platform · Jul 26, 2023 · bdea74c · bdea74c
1 parent 103bdf2
commit bdea74c
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Showing 2 changed files with 20 additions and 20 deletions.
diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv
@@ -361,17 +361,17 @@ module cheshire_top_xilinx
   // SPI Adaption //
   //////////////////
 
-  logic spi_sck_soc;
-  logic [1:0] spi_cs_soc;
-  logic [3:0] spi_sd_soc_out;
-  logic [3:0] spi_sd_soc_in;
-
-  logic spi_sck_en;
-  logic [1:0] spi_cs_en;
-  logic [3:0] spi_sd_en;
-  logic spi_sck_en_n;
-  logic [1:0] spi_cs_en_n;
-  logic [3:0] spi_sd_en_n;
+  (* mark_debug = "true" *) logic spi_sck_soc;
+  (* mark_debug = "true" *) logic [1:0] spi_cs_soc;
+  (* mark_debug = "true" *) logic [3:0] spi_sd_soc_out;
+  (* mark_debug = "true" *) logic [3:0] spi_sd_soc_in;
+
+  (* mark_debug = "true" *) logic spi_sck_en;
+  (* mark_debug = "true" *) logic [1:0] spi_cs_en;
+  (* mark_debug = "true" *) logic [3:0] spi_sd_en;
+  (* mark_debug = "true" *) logic spi_sck_en_n;
+  (* mark_debug = "true" *) logic [1:0] spi_cs_en_n;
+  (* mark_debug = "true" *) logic [3:0] spi_sd_en_n;
 
   //////////////////
   // SD           //
@@ -401,13 +401,13 @@ module cheshire_top_xilinx
   //////////////////
 
 `ifdef USE_QSPI
-  logic                 qspi_clk;
-  logic                 qspi_clk_ts;
-  logic [3:0]           qspi_dqi;
-  logic [3:0]           qspi_dqo_ts;
-  logic [3:0]           qspi_dqo;
-  logic [SpihNumCs-1:0] qspi_cs_b;
-  logic [SpihNumCs-1:0] qspi_cs_b_ts;
+  (* mark_debug = "true" *) logic                 qspi_clk;
+  (* mark_debug = "true" *) logic                 qspi_clk_ts;
+  (* mark_debug = "true" *) logic [3:0]           qspi_dqi;
+  (* mark_debug = "true" *) logic [3:0]           qspi_dqo_ts;
+  (* mark_debug = "true" *) logic [3:0]           qspi_dqo;
+  (* mark_debug = "true" *) logic [SpihNumCs-1:0] qspi_cs_b;
+  (* mark_debug = "true" *) logic [SpihNumCs-1:0] qspi_cs_b_ts;
 
   assign qspi_clk      = spi_sck_soc;
   assign qspi_cs_b     = spi_cs_soc;

diff --git a/target/xilinx/src/dram_wrapper.sv b/target/xilinx/src/dram_wrapper.sv
@@ -32,8 +32,8 @@ module dram_wrapper #(
     `DDR3_INTF
 `endif
     // Dram axi interface
-    (* mark_debug = "true" *) input  axi_soc_req_t  soc_req_i,
-    (* mark_debug = "true" *) output axi_soc_resp_t soc_rsp_o
+    input  axi_soc_req_t  soc_req_i,
+    output axi_soc_resp_t soc_rsp_o
 );
 
   ////////////////////////////////////