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Add vCLIC support
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ezelioli committed Jan 29, 2025
1 parent e2cc387 commit 325dcd9
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Showing 4 changed files with 33 additions and 11 deletions.
4 changes: 2 additions & 2 deletions Bender.lock
Original file line number Diff line number Diff line change
Expand Up @@ -69,8 +69,8 @@ packages:
- common_cells
- register_interface
clic:
revision: 8ed76ffc779a435d0ed034f3068e4c3334fe2ecf
version: 2.0.0
revision: f15060eda9d2c0a9597a80365d0344d87a92749a
version: null
source:
Git: https://github.com/pulp-platform/clic.git
dependencies:
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2 changes: 1 addition & 1 deletion Bender.yml
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Expand Up @@ -18,7 +18,7 @@ dependencies:
axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.2 }
axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git", version: 0.0.0-alpha.9 }
axi_vga: { git: "https://github.com/pulp-platform/axi_vga.git", version: 0.1.3 }
clic: { git: "https://github.com/pulp-platform/clic.git", version: 2.0.0 }
clic: { git: "https://github.com/pulp-platform/clic.git", rev: virt }
clint: { git: "https://github.com/pulp-platform/clint.git", version: 0.2.0 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.33.0 }
common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
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14 changes: 12 additions & 2 deletions hw/cheshire_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -214,6 +214,11 @@ package cheshire_pkg;
aw_bt AxiRtNumAddrRegions;
bit AxiRtCutPaths;
bit AxiRtEnableChecks;
// Parameters for CLIC
bit ClicVsclic;
bit ClicVsprio;
byte_bt ClicNumVsctxts;
aw_bt ClicPrioWidth;
} cheshire_cfg_t;

//////////////////
Expand Down Expand Up @@ -523,7 +528,7 @@ package cheshire_pkg;
ret.CachedRegionAddrBase = {AmSpm, cfg.LlcOutRegionStart, CieBase};
ret.CachedRegionLength = {SizeSpm, SizeLlcOut, cfg.Cva6ExtCieLength};
ret.RVSCLIC = cfg.Clic;
ret.RVVCLIC = 0;
ret.RVVCLIC = cfg.ClicVsclic;
ret.CLICNumInterruptSrc = NumCoreIrqs + NumIntIntrs + cfg.NumExtClicIntrs;
ret.RASDepth = cfg.Cva6RASDepth;
ret.BTBEntries = cfg.Cva6BTBEntries;
Expand Down Expand Up @@ -629,7 +634,7 @@ package cheshire_pkg;
Vga : 1,
Usb : 1,
AxiRt : 0,
Clic : 0,
Clic : 1,
IrqRouter : 0,
BusErr : 1,
// Debug
Expand Down Expand Up @@ -689,6 +694,11 @@ package cheshire_pkg;
AxiRtWBufferDepth : 16,
AxiRtNumAddrRegions : 2,
AxiRtCutPaths : 1,
// CLIC
ClicVsclic : 1,
ClicVsprio : 1,
ClicNumVsctxts : 4,
ClicPrioWidth : 1,
// All non-set values should be zero
default: '0
};
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24 changes: 18 additions & 6 deletions hw/cheshire_soc.sv
Original file line number Diff line number Diff line change
Expand Up @@ -598,6 +598,8 @@ module cheshire_soc import cheshire_pkg::*; #(
logic [$clog2(NumClicIntrs)-1:0] clic_irq_id;
logic [7:0] clic_irq_level;
riscv::priv_lvl_t clic_irq_priv;
logic clic_irq_v;
logic [5:0] clic_irq_vsid;

cva6 #(
.CVA6Cfg ( build_config_pkg::build_config(Cva6Cfg) ),
Expand All @@ -621,6 +623,8 @@ module cheshire_soc import cheshire_pkg::*; #(
.clic_irq_id_i ( clic_irq_id ),
.clic_irq_level_i ( clic_irq_level ),
.clic_irq_priv_i ( clic_irq_priv ),
.clic_irq_v_i ( clic_irq_v ),
.clic_irq_vsid_i ( clic_irq_vsid ),
.clic_irq_shv_i ( clic_irq_shv ),
.clic_irq_ready_o ( clic_irq_ready ),
.clic_kill_req_i ( clic_irq_kill_req ),
Expand Down Expand Up @@ -675,12 +679,16 @@ module cheshire_soc import cheshire_pkg::*; #(
};

clic #(
.N_SOURCE ( NumClicIntrs ),
.INTCTLBITS ( Cfg.ClicIntCtlBits ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t ),
.SSCLIC ( 1 ),
.USCLIC ( 0 )
.N_SOURCE ( NumClicIntrs ),
.INTCTLBITS ( Cfg.ClicIntCtlBits ),
.reg_req_t ( reg_req_t ),
.reg_rsp_t ( reg_rsp_t ),
.SSCLIC ( 1 ),
.USCLIC ( 0 ),
.VSCLIC ( Cfg.ClicVsclic ),
.N_VSCTXTS ( Cfg.ClicNumVsctxts ),
.VSPRIO ( Cfg.ClicVsprio ),
.VsprioWidth ( Cfg.ClicPrioWidth )
) i_clic (
.clk_i,
.rst_ni,
Expand All @@ -693,6 +701,8 @@ module cheshire_soc import cheshire_pkg::*; #(
.irq_level_o ( clic_irq_level ),
.irq_shv_o ( clic_irq_shv ),
.irq_priv_o ( clic_irq_priv ),
.irq_v_o ( clic_irq_v ),
.irq_vsid_o ( clic_irq_vsid ),
.irq_kill_req_o ( clic_irq_kill_req ),
.irq_kill_ack_i ( clic_irq_kill_ack )
);
Expand All @@ -704,6 +714,8 @@ module cheshire_soc import cheshire_pkg::*; #(
assign clic_irq_level = '0;
assign clic_irq_shv = '0;
assign clic_irq_priv = riscv::priv_lvl_t'(0);
assign clic_irq_v = '0;
assign clic_irq_vsid = '0;
assign clic_irq_kill_req = '0;

end
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