MIPS-QEMU 2.2.0.1.0

MIPS QEMU v2.2.0.1.0 release note

• Overview
  MIPS QEMU based on prpl Foundation QEMU
• New features in this release
  Hardware page Table Walker (MIPS32 only)
  Misaligned Memory Accesses for R6 and MSA
  Large Physical Address (MIPS64)
  Load-Linked Bit (Config5.LLB)
  User Mode .MIPS.abiflags support
  Fixed fexdo, fexupl and fexupr MSA instructions
  Fixed R6 and MSA implementation issues
  Renamed MIPS64R6-generic into I6400
• Features removed in this release
  Static IEEE 754-2008 support - Dynamic version of the feature has been submitted to Upstream
  R6/R5 hybrid mode option (MIPS_R6R5_HYBRID_USER) - Experimental feature
  MIPS64-generic-msa, MIPS32R5-generic-fre CPU definitions - Features are available for I6400 and P5600 instead
• Version based
  Upstream version of QEMU v2.2.0
  prpl Foundation QEMU PRIP3 and PRIP4
• Limitation
  Following MSA instructions have not been fully verified:
  msa_flog2.{d,w}, msa_ftint_u.{d,w}, msa_ftrunc_u.{d,w}
  TLB duplicate Machine Check is not performed
• Known issues

* Release History

• Features added at v2.0.0.3.0
  MIPS32/64 SIMD Architecture Module - performance improved
  FRE support (New CPU definition "MIPS32R5-generic-fre" and updated "MIPS64R6-generic")
  R6/R5 hybrid mode option added (MIPS_R6R5_HYBRID_USER)
  Fixed broken MIPS16 and microMIPS
  Fixed some corner cases FP underflow signalling
  Fixed issue of MSA and POSIX Threads (PThreads) on user mode
• Features added at v2.0.0.2
  MIPS32R5 support (apart from VZ) including 40Bit XPA, MAAR (registers only), Hardware Page Table Walker (registers only)
  MIPS32/64 SIMD Architecture Module
  New CPU definition "P5600" providing R5 features
  New CPU definition "MIPS64R6-generic-msa" providing MSA feature on MIPS64R6
• Feature added at v2.0.0.1
  MIPS64R6 support (including R5 features which are mandatory in R6)
  New CPU definition "MIPS64R6-generic" and "MIPS32R6-generic" providing R6 features