drm/i915/gvt: Fixed an issue in PS MMIO handlers

When GVT-g guest tries to disable a scaler, it will write 0 to PS_CTRL register. However, in such case, GVT-g PS MMIO handler will not allow this value to be written to the HW, which will cause scaler cannot be disabled. This patch fixed the issue mentioned above. V2: Uses PS_SCALER_EN to check if scaler is enabled. Tracked-on: projectacrn/acrn-hypervisor#1188 Signed-off-by: Min He <[email protected]> Signed-off-by: Fei Jiang <[email protected]> Reviewed-by: Zhao Yakui <[email protected]>
projectacrn · Sep 10, 2018 · 7feffb6 · 7feffb6
1 parent 486488a
commit 7feffb6
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -845,9 +845,9 @@ static int skl_ps_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
 	if (!(vgpu_vreg(vgpu, PIPECONF(pipe)) & I965_PIPECONF_ACTIVE))
 		return 0;
 
-	if (offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
+	if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
 	   offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
-	   offset == _PS_1C_CTRL) {
+	   offset == _PS_1C_CTRL) && ((*(u32 *)p_data) & PS_SCALER_EN)) {
 		unsigned int plane;
 
 		if (SKL_PS_REG_VALUE_TO_PLANE(*(u32 *)p_data) == 0) {