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Attempt to reduce CI failures in Energy Reporting test cases #34318
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Attempt to reduce CI failures in Energy Reporting test cases #34318
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…readings have changed.
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PR #34318: Size comparison from a5d8f62 to 42d36e9 Full report (85 builds for bl602, bl702, bl702l, cc13x4_26x4, cc32xx, cyw30739, efr32, esp32, linux, mbed, nrfconnect, nxp, psoc6, qpg, stm32, telink, tizen)
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…readings have changed. (project-chip#34318)
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Over the last few months there seems to have been more and more CI failures caused by
the tests in EEM and EPM when checking for 2 values to be different.
There are 2 test event triggers (one generates readings every 2s, one generates them every 5s).
The idea of the tests was to trigger the fake readings, and then wait the repeat period +1s which should have been ample time for a CPU to handle any jitter.
Observations seem to be that the CI platform VMs can starve the processors for >300ms, so a couple of these starvations could push the test to fail.
In an attempt to prove if this is the root cause, then we have proposed doubling the wait time to be 2 x repeat_period + 1s.
i.e. where we had a wait 3s -> wait 5s (for 2s updates)
i.e. where we had a wait 6s -> wait 11s (for 5s updates).
This impacts several scripts in EEM and EPM clusters.
[Test cases will need to be updated separately IF this seems to be a solution - see Test Plan issue https://github.com/CHIP-Specifications/chip-test-plans/issues/4284]