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Cache bootstrap step in all CI workflows #24968

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merged 5 commits into from
Feb 14, 2023
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@arkq arkq commented Feb 10, 2023

Problem

Bootstrap takes ~5-6min to complete and is used in almost all workflows. Caching this step can save ~4-5min (restore takes ~1min).

Changes

  • moved all bootstrap configuration files to a dedicated directory (the hash of these files will be used as a cache key)
  • added cache step before bootstrap step in workflow files
  • use action cache feature for caching PyPi files (this will generate proper cache key - based on requirements content)

Testing

CI will test that in a 2 steps process:

  1. PR check should pass during initial check
  2. PR check should pass after merging master changes (on second run, cache should be used for bootstrap step)

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PR #24968: Size comparison from 1f81384 to b102b1a

Increases (2 builds for bl602, bl702)
platform target config section 1f81384 b102b1a change % change
bl602 lighting-app bl602+rpc (read/write) 1392014 1392022 8 0.0
.text 1054254 1054258 4 0.0
bl702 lighting-app bl702+rpc .debug_info 44938489 44938491 2 0.0
.text 1029628 1029632 4 0.0
Decreases (1 build for qpg)
platform target config section 1f81384 b102b1a change % change
qpg lock-app qpg6105+debug (read/write) 1116736 1116728 -8 -0.0
.text 563832 563824 -8 -0.0
Full report (7 builds for bl602, bl702, cc32xx, qpg)
platform target config section 1f81384 b102b1a change % change
bl602 lighting-app bl602 (read/write) 1346582 1346582 0 0.0
.bss 94794 94794 0 0.0
.data 9736 9736 0 0.0
.text 1023324 1023324 0 0.0
bl602+rpc (read/write) 1392014 1392022 8 0.0
.bss 102842 102842 0 0.0
.data 10128 10128 0 0.0
.text 1054254 1054258 4 0.0
bl702 lighting-app bl702 0 0 0 0.0
(read only) 3358 3358 0 0.0
(read/write) 1184651 1184651 0 0.0
.bleromro 6342 6342 0 0.0
.bleromrw 124 124 0 0.0
.boot2 292 292 0 0.0
.bss 69905 69905 0 0.0
.bss_psram 30048 30048 0 0.0
.comment 48 48 0 0.0
.data 4056 4056 0 0.0
.debug_abbrev 1550382 1550382 0 0.0
.debug_aranges 134192 134192 0 0.0
.debug_frame 491492 491492 0 0.0
.debug_info 4053630 4053630 0 0.0
.debug_line 5272965 5272965 0 0.0
.debug_loc 3409446 3409446 0 0.0
.debug_ranges 371752 371752 0 0.0
.debug_str 3558337 3558337 0 0.0
.hbn 536 536 0 0.0
.hbn_noinit 260 260 0 0.0
.init 342 342 0 0.0
.init_array 144 144 0 0.0
.psram 0 0 0 0.0
.riscv.attributes 47 47 0 0.0
.rodata 107120 107120 0 0.0
.rsvd 2960 2960 0 0.0
.sha_ocram 72 72 0 0.0
.shstrtab 304 304 0 0.0
.stack 2048 2048 0 0.0
.strtab 572518 572518 0 0.0
.symtab 173424 173424 0 0.0
.tcm_data 36 36 0 0.0
.tcmcode 3358 3358 0 0.0
.text 952436 952436 0 0.0
bl702+rpc 0 0 0 0.0
(read only) 3358 3358 0 0.0
(read/write) 1277535 1277535 0 0.0
.bleromro 6342 6342 0 0.0
.bleromrw 124 124 0 0.0
.boot2 292 292 0 0.0
.bss 77953 77953 0 0.0
.bss_psram 30304 30304 0 0.0
.comment 48 48 0 0.0
.data 4608 4608 0 0.0
.debug_abbrev 1698796 1698796 0 0.0
.debug_aranges 142424 142424 0 0.0
.debug_frame 519236 519236 0 0.0
.debug_info 44938489 44938491 2 0.0
.debug_line 5671672 5671672 0 0.0
.debug_loc 3606205 3606205 0 0.0
.debug_ranges 395520 395520 0 0.0
.debug_str 3961701 3961701 0 0.0
.hbn 536 536 0 0.0
.hbn_noinit 260 260 0 0.0
.init 342 342 0 0.0
.init_array 160 160 0 0.0
.psram 0 0 0 0.0
.riscv.attributes 47 47 0 0.0
.rodata 121696 121696 0 0.0
.rsvd 2960 2960 0 0.0
.sha_ocram 72 72 0 0.0
.shstrtab 304 304 0 0.0
.stack 2048 2048 0 0.0
.strtab 633311 633311 0 0.0
.symtab 191840 191840 0 0.0
.tcm_data 36 36 0 0.0
.tcmcode 3358 3358 0 0.0
.text 1029628 1029632 4 0.0
cc32xx lock CC3235SF_LAUNCHXL 0 0 0 0.0
(read only) 640233 640233 0 0.0
(read/write) 204084 204084 0 0.0
.ARM.attributes 44 44 0 0.0
.ARM.exidx 8 8 0 0.0
.bss 197488 197488 0 0.0
.comment 194 194 0 0.0
.data 1476 1476 0 0.0
.debug_abbrev 928439 928439 0 0.0
.debug_aranges 87352 87352 0 0.0
.debug_frame 299840 299840 0 0.0
.debug_info 20194396 20194396 0 0.0
.debug_line 2649797 2649797 0 0.0
.debug_loc 2785922 2785922 0 0.0
.debug_ranges 280720 280720 0 0.0
.debug_str 3001474 3001474 0 0.0
.ramVecs 780 780 0 0.0
.resetVecs 64 64 0 0.0
.rodata 105585 105585 0 0.0
.shstrtab 232 232 0 0.0
.stab 204 204 0 0.0
.stabstr 441 441 0 0.0
.stack 2048 2048 0 0.0
.strtab 375840 375840 0 0.0
.symtab 255856 255856 0 0.0
.text 532524 532524 0 0.0
qpg lighting-app qpg6105+debug (read/write) 1148688 1148688 0 0.0
.bss 99876 99876 0 0.0
.data 848 848 0 0.0
.text 595788 595788 0 0.0
lock-app qpg6105+debug (read/write) 1116736 1116728 -8 -0.0
.bss 96396 96396 0 0.0
.data 860 860 0 0.0
.text 563832 563824 -8 -0.0

@andy31415 andy31415 merged commit 3d9bc88 into project-chip:master Feb 14, 2023
lecndav pushed a commit to lecndav/connectedhomeip that referenced this pull request Mar 22, 2023
* Move bootstrap configuration files to separate dir

Keeping all files used to bootstrap the project in a dedicated directory
will simplify environment cache invalidation.

* Compatibility for old location of bootstrap script

* Cache bootstrap step in all CI workflows

* Update constraints location in config files

* Hash all pigweed files when creating cache key
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3 participants