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Added simulated tests Dec 09 #24000
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andy31415
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project-chip:master
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manjunath-grl:Added_Simulated_test_Dec_09
Dec 13, 2022
Merged
Added simulated tests Dec 09 #24000
andy31415
merged 3 commits into
project-chip:master
from
manjunath-grl:Added_Simulated_test_Dec_09
Dec 13, 2022
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PR #24000: Size comparison from f54f0f6 to 7feea8f Increases (6 builds for cc13x2_26x2, psoc6, telink)
Decreases (7 builds for bl602, cc13x2_26x2, linux, psoc6, telink)
Full report (53 builds for bl602, bl702, cc13x2_26x2, cyw30739, efr32, esp32, k32w, linux, mbed, nrfconnect, psoc6, qpg, telink)
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PR #24000: Size comparison from a7060e0 to 456424b Increases (2 builds for bl702, telink)
Decreases (6 builds for cyw30739, esp32, linux, telink)
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Fixes #23834
Added simulated tests
TC_ACT_3_1_Simulated
TC_BOOL_3_1_Simulated
TC_DESC_2_2_Simulated
TC_DGETH_3_1_Simulated
TC_DGETH_3_2_Simulated
TC_DGSW_3_1_Simulated
TC_DGSW_3_2_Simulated
TC_DGWIFI_3_1_Simulated
TC_DGWIFI_3_2_Simulated
TC_FLW_3_1_Simulated
TC_G_3_1_Simulated
TC_I_3_1_Simulated
TC_PRS_3_1_Simulated
TC_PS_3_1_Simulated
TC_PSCFG_3_1_Simulated
TC_RH_3_1_Simulated
TC_SWTCH_3_1_Simulated
TC_WNCV_5_1_Simulated
Added auto generated files
Testsed
execution logs:
All_tests_logs.zip