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Update uctags.vim
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Add for systemverilog.  Accdording to https://docs.ctags.io/en/latest/man/ctags-lang-verilog.7.html
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@sqlmap3
sqlmap3 authored Jul 24, 2024
1 parent 0815b54 commit 42d4eda
Showing 1 changed file with 36 additions and 0 deletions.
36 changes: 36 additions & 0 deletions autoload/tagbar/types/uctags.vim
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Original file line number Diff line number Diff line change
Expand Up @@ -1332,6 +1332,42 @@ function! tagbar#types#uctags#init(supported_types) abort
\ {'short' : 't', 'long' : 'tasks', 'fold' : 0, 'stl' : 1}
\ ]
let types.verilog = type_verilog
" SystemVerilog {{{1
let type_systemverilog = tagbar#prototypes#typeinfo#new()
let type_systemverilog.ctagstype = 'systemverilog'
let type_systemverilog.kinds = [
\ {'short' : 'A', 'long' : 'assertions(assert,assume,cover,restrict)', 'fold' : 0, 'stl' : 1},
\ {'short' : 'C', 'long' : 'classes', 'fold' : 0, 'stl' : 1},
\ {'short' : 'E', 'long' : 'enumerators', 'fold' : 0, 'stl' : 1},
\ {'short' : 'H', 'long' : 'checkers', 'fold' : 0, 'stl' : 1},
\ {'short' : 'I', 'long' : 'interfaces', 'fold' : 0, 'stl' : 1},
\ {'short' : 'K', 'long' : 'packages', 'fold' : 1, 'stl' : 0},
\ {'short' : 'L', 'long' : 'clokcing', 'fold' : 0, 'stl' : 1},
\ {'short' : 'M', 'long' : 'modports', 'fold' : 0, 'stl' : 1},
\ {'short' : 'N', 'long' : 'nettype declarations', 'fold' : 0, 'stl' : 0},
\ {'short' : 'O', 'long' : 'constraints', 'fold' : 0, 'stl' : 1},
\ {'short' : 'P', 'long' : 'programs', 'fold' : 0, 'stl' : 1},
\ {'short' : 'Q', 'long' : 'prototypes(extern,pure)', 'fold' : 0, 'stl' : 1},
\ {'short' : 'R', 'long' : 'properties', 'fold' : 0, 'stl' : 1},
\ {'short' : 'S', 'long' : 'structs and unions', 'fold' : 0, 'stl' : 1},
\ {'short' : 'T', 'long' : 'type declarations', 'fold' : 0, 'stl' : 1},
\ {'short' : 'V', 'long' : 'covergroups', 'fold' : 0, 'stl' : 1},
\ {'short' : 'b', 'long' : 'blocks(begin,fork)', 'fold' : 0, 'stl' : 1},
\ {'short' : 'c', 'long' : 'constants(paramter,specparam,enum values)', 'fold' : 0, 'stl' : 0},
\ {'short' : 'd', 'long' : 'text macros', 'fold' : 0, 'stl' : 1},
\ {'short' : 'e', 'long' : 'events', 'fold' : 0, 'stl' : 1},
\ {'short' : 'f', 'long' : 'functions', 'fold' : 0, 'stl' : 1},
\ {'short' : 'i', 'long' : 'instances of module or interface', 'fold' : 0, 'stl' : 1},
\ {'short' : 'l', 'long' : 'interface class', 'fold' : 0, 'stl' : 1},
\ {'short' : 'm', 'long' : 'modules', 'fold' : 0, 'stl' : 1},
\ {'short' : 'n', 'long' : 'net data types', 'fold' : 0, 'stl' : 0},
\ {'short' : 'p', 'long' : 'ports', 'fold' : 1, 'stl' : 1},
\ {'short' : 'q', 'long' : 'sequences', 'fold' : 0, 'stl' : 1},
\ {'short' : 'r', 'long' : 'variable data types', 'fold' : 1, 'stl' : 1},
\ {'short' : 't', 'long' : 'tasks', 'fold' : 0, 'stl' : 1},
\ {'short' : 'w', 'long' : 'struct and union members ', 'fold' : 0, 'stl' : 1}
\ ]
let types.systemverilog = type_systemverilog
" VHDL {{{1
" The VHDL ctags parser unfortunately doesn't generate proper scopes
let type_vhdl = tagbar#prototypes#typeinfo#new()
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