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postoroniy/bluespec-reedsolomon

 
 

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Top level files

  • for the decoder: mkReedSolomon.bsv
  • Top level testbench: mkTestbench.bsv

Testbench

Test file is generated by python, where 2 symbols are corrupted, which for decoder RS(255,251) should not be the issue to recover. The testbench reads the corrupted data from the file input.dat (with the first 2 terms being 'n' and 't' parameters) and writes the decoded output to output.dat. If files output.dat and ref_output.dat are matched simulation deemed to be successful.

Synthesys

Yosys is used for synthesys and estimation of FFs, LUTs and etc. Default FPGA family is "Ultrascale Plus" can be changed in ys file.

Installations required:

  • Bluespec compiler
  • yosys for synthesys

What is missed

All C sources of RS decoder were removed and model of decoder in python is in progress.

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Bluespec SystemVerilog Reed Solomon Decoder

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  • Bluespec 75.9%
  • C++ 13.8%
  • Python 5.5%
  • Makefile 4.8%