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TGL-H GPIOs Workaround #71

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merged 4 commits into from
Sep 16, 2021
Merged

TGL-H GPIOs Workaround #71

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7ffd196
ALSA: hda/realtek: Add fixup for oryp8
crawfxrd Sep 14, 2021
0688190
pinctrl: tigerlake: Fix GPIO mapping for newer version of software
andy-shev Aug 4, 2021
6a0e5e3
pinctrl: Export intel_pinctrl_probe
jackpot51 Sep 14, 2021
930e87c
pinctrl: tigerlake: Workaround for old communities on System76 gaze16
jackpot51 Sep 14, 2021
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5 changes: 3 additions & 2 deletions drivers/pinctrl/intel/pinctrl-intel.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1456,8 +1456,8 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl)
return 0;
}

static int intel_pinctrl_probe(struct platform_device *pdev,
const struct intel_pinctrl_soc_data *soc_data)
int intel_pinctrl_probe(struct platform_device *pdev,
const struct intel_pinctrl_soc_data *soc_data)
{
struct intel_pinctrl *pctrl;
int i, ret, irq;
Expand Down Expand Up @@ -1571,6 +1571,7 @@ static int intel_pinctrl_probe(struct platform_device *pdev,

return 0;
}
EXPORT_SYMBOL_GPL(intel_pinctrl_probe);

int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
{
Expand Down
2 changes: 2 additions & 0 deletions drivers/pinctrl/intel/pinctrl-intel.h
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Original file line number Diff line number Diff line change
Expand Up @@ -244,6 +244,8 @@ struct intel_pinctrl {
int irq;
};

int intel_pinctrl_probe(struct platform_device *pdev,
const struct intel_pinctrl_soc_data *soc_data);
int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
int intel_pinctrl_probe_by_uid(struct platform_device *pdev);

Expand Down
81 changes: 75 additions & 6 deletions drivers/pinctrl/intel/pinctrl-tigerlake.c
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,8 @@

#include <linux/pinctrl/pinctrl.h>

#include <linux/dmi.h>

#include "pinctrl-intel.h"

#define TGL_PAD_OWN 0x020
Expand Down Expand Up @@ -699,37 +701,104 @@ static const struct pinctrl_pin_desc tglh_pins[] = {
PINCTRL_PIN(290, "CPU_TRSTB"),
};

static const struct intel_padgroup tglh_community0_gpps[] = {
static const struct intel_padgroup tglh_old_community0_gpps[] = {
TGL_GPP(0, 0, 24, 0), /* GPP_A */
TGL_GPP(1, 25, 44, 128), /* GPP_R */
TGL_GPP(2, 45, 70, 32), /* GPP_B */
TGL_GPP(3, 71, 78, INTEL_GPIO_BASE_NOMAP), /* vGPIO_0 */
};

static const struct intel_padgroup tglh_community1_gpps[] = {
static const struct intel_padgroup tglh_old_community1_gpps[] = {
TGL_GPP(0, 79, 104, 96), /* GPP_D */
TGL_GPP(1, 105, 128, 64), /* GPP_C */
TGL_GPP(2, 129, 136, 160), /* GPP_S */
TGL_GPP(3, 137, 153, 192), /* GPP_G */
TGL_GPP(4, 154, 180, 224), /* vGPIO */
};

static const struct intel_padgroup tglh_community3_gpps[] = {
static const struct intel_padgroup tglh_old_community3_gpps[] = {
TGL_GPP(0, 181, 193, 256), /* GPP_E */
TGL_GPP(1, 194, 217, 288), /* GPP_F */
};

static const struct intel_padgroup tglh_community4_gpps[] = {
static const struct intel_padgroup tglh_old_community4_gpps[] = {
TGL_GPP(0, 218, 241, 320), /* GPP_H */
TGL_GPP(1, 242, 251, 384), /* GPP_J */
TGL_GPP(2, 252, 266, 352), /* GPP_K */
};

static const struct intel_padgroup tglh_community5_gpps[] = {
static const struct intel_padgroup tglh_old_community5_gpps[] = {
TGL_GPP(0, 267, 281, 416), /* GPP_I */
TGL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP), /* JTAG */
};

static const struct intel_community tglh_old_communities[] = {
TGL_H_COMMUNITY(0, 0, 78, tglh_old_community0_gpps),
TGL_H_COMMUNITY(1, 79, 180, tglh_old_community1_gpps),
TGL_H_COMMUNITY(2, 181, 217, tglh_old_community3_gpps),
TGL_H_COMMUNITY(3, 218, 266, tglh_old_community4_gpps),
TGL_H_COMMUNITY(4, 267, 290, tglh_old_community5_gpps),
};

static const struct intel_pinctrl_soc_data tglh_old_soc_data = {
.pins = tglh_pins,
.npins = ARRAY_SIZE(tglh_pins),
.communities = tglh_old_communities,
.ncommunities = ARRAY_SIZE(tglh_old_communities),
};

static int tgl_pinctrl_probe(struct platform_device *pdev)
{
const struct intel_pinctrl_soc_data *data;

data = device_get_match_data(&pdev->dev);
if (!data)
return -ENODATA;

/*
* The first System76 gaze16 firmware had an older version of
* the TGL-H GPIO table, before it was normalized with Windows.
*/
if (dmi_match(DMI_SYS_VENDOR, "System76") &&
(dmi_match(DMI_PRODUCT_VERSION, "gaze16-3050") ||
dmi_match(DMI_PRODUCT_VERSION, "gaze16-3060")) &&
dmi_match(DMI_BIOS_VERSION, "2021-07-20_93c2809"))
data = &tglh_old_soc_data;

return intel_pinctrl_probe(pdev, data);
}

static const struct intel_padgroup tglh_community0_gpps[] = {
TGL_GPP(0, 0, 24, 0), /* GPP_A */
TGL_GPP(1, 25, 44, 32), /* GPP_R */
TGL_GPP(2, 45, 70, 64), /* GPP_B */
TGL_GPP(3, 71, 78, 96), /* vGPIO_0 */
};

static const struct intel_padgroup tglh_community1_gpps[] = {
TGL_GPP(0, 79, 104, 128), /* GPP_D */
TGL_GPP(1, 105, 128, 160), /* GPP_C */
TGL_GPP(2, 129, 136, 192), /* GPP_S */
TGL_GPP(3, 137, 153, 224), /* GPP_G */
TGL_GPP(4, 154, 180, 256), /* vGPIO */
};

static const struct intel_padgroup tglh_community3_gpps[] = {
TGL_GPP(0, 181, 193, 288), /* GPP_E */
TGL_GPP(1, 194, 217, 320), /* GPP_F */
};

static const struct intel_padgroup tglh_community4_gpps[] = {
TGL_GPP(0, 218, 241, 352), /* GPP_H */
TGL_GPP(1, 242, 251, 384), /* GPP_J */
TGL_GPP(2, 252, 266, 416), /* GPP_K */
};

static const struct intel_padgroup tglh_community5_gpps[] = {
TGL_GPP(0, 267, 281, 448), /* GPP_I */
TGL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP), /* JTAG */
};

static const struct intel_community tglh_communities[] = {
TGL_H_COMMUNITY(0, 0, 78, tglh_community0_gpps),
TGL_H_COMMUNITY(1, 79, 180, tglh_community1_gpps),
Expand All @@ -756,7 +825,7 @@ MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match);
static INTEL_PINCTRL_PM_OPS(tgl_pinctrl_pm_ops);

static struct platform_driver tgl_pinctrl_driver = {
.probe = intel_pinctrl_probe_by_hid,
.probe = tgl_pinctrl_probe,
.driver = {
.name = "tigerlake-pinctrl",
.acpi_match_table = tgl_pinctrl_acpi_match,
Expand Down
2 changes: 2 additions & 0 deletions sound/pci/hda/patch_realtek.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2548,6 +2548,8 @@ static const struct snd_pci_quirk alc882_fixup_tbl[] = {
SND_PCI_QUIRK(0x1558, 0x67e1, "Clevo PB71[DE][CDF]", ALC1220_FIXUP_CLEVO_PB51ED_PINS),
SND_PCI_QUIRK(0x1558, 0x67e5, "Clevo PC70D[PRS](?:-D|-G)?", ALC1220_FIXUP_CLEVO_PB51ED_PINS),
SND_PCI_QUIRK(0x1558, 0x70d1, "Clevo PC70[ER][CDF]", ALC1220_FIXUP_CLEVO_PB51ED_PINS),
SND_PCI_QUIRK(0x1558, 0x65f1, "System76 Oryx Pro (oryp8)", ALC1220_FIXUP_CLEVO_PB51ED_PINS),
SND_PCI_QUIRK(0x1558, 0x67f1, "System76 Oryx Pro (oryp8)", ALC1220_FIXUP_CLEVO_PB51ED_PINS),
SND_PCI_QUIRK(0x1558, 0x7714, "Clevo X170", ALC1220_FIXUP_CLEVO_PB51ED_PINS),
SND_PCI_QUIRK(0x1558, 0x9501, "Clevo P950HR", ALC1220_FIXUP_CLEVO_P950),
SND_PCI_QUIRK(0x1558, 0x9506, "Clevo P955HQ", ALC1220_FIXUP_CLEVO_P950),
Expand Down