hal: AArch64/ZynqMP port #635

jmaksymowicz · 2025-01-30T15:26:31Z

Port plo to AArch64 architecture and Zynq Ultrascale platform.

Description

Motivation and Context

Types of changes

Bug fix (non-breaking change which fixes an issue)
New feature (non-breaking change which adds functionality)
Breaking change (fix or feature that would cause existing functionality to change)
Chore (refactoring, style fixes, git/CI config, submodule management, no code logic changes)

How Has This Been Tested?

Already covered by automatic testing.
New test added: (add PR link here).
Tested by hand on: aarch64-zynqmp-qemu

Checklist:

My change requires a change to the documentation.
I have updated the documentation accordingly.
I have added tests to cover my changes.
All new and existing linter checks and tests passed.
My changes generate no new compilation warnings for any of the targets.

Special treatment

This PR needs additional PRs to work (list the PRs, preferably in merge-order).
I will merge this PR by myself when appropriate.

Due to exiting on different stack than current's thread in fork in child the return value was not set by threads_setupUserReturn. JIRA: RTOS-979

github-actions · 2025-01-30T15:26:48Z

hal/aarch64/aarch64.h

+		__asm__ volatile ( \
+			"msr " #sysreg ", %0" \
+			: \
+			: "r"(__v) \
+			: "memory"); \


[clang-format-pr] _{reported by reviewdog 🐶}
suggested fix

Suggested change

__asm__ volatile ( \

"msr " #sysreg ", %0" \

: \

: "r"(__v) \

: "memory"); \

__asm__ volatile( \

"msr " #sysreg ", %0" \

: \

: "r"(__v) \

: "memory"); \

github-actions · 2025-01-30T15:26:48Z

hal/aarch64/aarch64.h

+		__asm__ volatile ( \
+			"mrs %0, " #sysreg \
+			: "=r"(__v) \
+			: \
+			: "memory"); \


[clang-format-pr] _{reported by reviewdog 🐶}
suggested fix

Suggested change

__asm__ volatile ( \

"mrs %0, " #sysreg \

: "=r"(__v) \

: \

: "memory"); \

__asm__ volatile( \

"mrs %0, " #sysreg \

: "=r"(__v) \

: \

: "memory"); \

github-actions · 2025-01-30T15:26:48Z

hal/aarch64/aarch64.h

+
+static inline void hal_cpuDataMemoryBarrier(void)
+{
+	__asm__ volatile ("dmb ish");


[clang-format-pr] _{reported by reviewdog 🐶}
suggested fix

Suggested change

__asm__ volatile ("dmb ish");

__asm__ volatile("dmb ish");

github-actions · 2025-01-30T15:26:48Z

hal/aarch64/aarch64.h

+
+static inline void hal_cpuDataSyncBarrier(void)
+{
+	__asm__ volatile ("dsb ish");


[clang-format-pr] _{reported by reviewdog 🐶}
suggested fix

Suggested change

__asm__ volatile ("dsb ish");

__asm__ volatile("dsb ish");

github-actions · 2025-01-30T15:26:48Z

hal/aarch64/aarch64.h

+
+static inline void hal_cpuDataSyncBarrierSys(void)
+{
+	__asm__ volatile ("dsb sy");


[clang-format-pr] _{reported by reviewdog 🐶}
suggested fix

Suggested change

__asm__ volatile ("dsb sy");

__asm__ volatile("dsb sy");

github-actions · 2025-01-30T15:26:49Z

hal/aarch64/aarch64.h

+static inline void hal_tlbInvalVA_IS(ptr_t vaddr)
+{
+	u64 arg = (vaddr >> 12) & ((1uL << 44) - 1);
+	__asm__ volatile ("tlbi vaae1is, %0" : : "r"(arg));


[clang-format-pr] _{reported by reviewdog 🐶}
suggested fix

Suggested change

__asm__ volatile ("tlbi vaae1is, %0" : : "r"(arg));

__asm__ volatile("tlbi vaae1is, %0" : : "r"(arg));

github-actions · 2025-01-30T15:26:49Z

hal/aarch64/aarch64.h

+static inline void hal_tlbInvalVAASID_IS(ptr_t vaddr, asid_t asid)
+{
+	u64 arg = ((vaddr >> 12) & ((1uL << 44) - 1)) | ((u64)asid << 48);
+	__asm__ volatile ("tlbi vae1is, %0" : : "r"(arg));


[clang-format-pr] _{reported by reviewdog 🐶}
suggested fix

Suggested change

__asm__ volatile ("tlbi vae1is, %0" : : "r"(arg));

__asm__ volatile("tlbi vae1is, %0" : : "r"(arg));

github-actions · 2025-01-30T15:26:49Z

hal/aarch64/aarch64.h

+/* Invalidate entire Unified TLB (broadcast to Inner Shareable domain) */
+static inline void hal_tlbInvalAll_IS(void)
+{
+	__asm__ volatile ("tlbi vmalle1is");


[clang-format-pr] _{reported by reviewdog 🐶}
suggested fix

Suggested change

__asm__ volatile ("tlbi vmalle1is");

__asm__ volatile("tlbi vmalle1is");

github-actions · 2025-01-30T15:26:49Z

hal/aarch64/aarch64.h

+
+struct aarch64_proc_id {
+	u64 mmfr0; /* ID_AA64MMFR0_EL1 */
+	u64 pfr0; /* ID_AA64PFR0_EL1 */


[clang-format-pr] _{reported by reviewdog 🐶}
suggested fix

Suggested change

u64 pfr0; /* ID_AA64PFR0_EL1 */

u64 pfr0; /* ID_AA64PFR0_EL1 */

github-actions · 2025-01-30T15:26:49Z

hal/aarch64/aarch64.h

+	u32 dfr0; /* ID_AA64DFR0_EL1 */
+	u32 midr; /* MIDR_EL1 */


[clang-format-pr] _{reported by reviewdog 🐶}
suggested fix

Suggested change

u32 dfr0; /* ID_AA64DFR0_EL1 */

u32 midr; /* MIDR_EL1 */

u32 dfr0; /* ID_AA64DFR0_EL1 */

u32 midr; /* MIDR_EL1 */

github-actions · 2025-01-30T15:26:55Z

hal/aarch64/_exceptions.S

+_exceptions_checkFPUTrap:
+#ifndef __SOFTFP__
+	lsr w26, W_ESR_EL1, #26
+	cmp w26, #0x7 /* SME, SVE, SIMD or FP trapped due to CPACR_EL1 */


[codespell] _{reported by reviewdog 🐶}
SME ==> SAME, SEME, SOME, SMS

github-actions · 2025-01-30T15:26:56Z

hal/aarch64/exceptions.c

+		case 0b000110:
+			return "Trapped LDC/STC access";
+		case 0b000111:
+			return "Trapped SME, SVE, Advanced SIMD or floating-point functionality due to CPACR_ELx.FPEN";


[codespell] _{reported by reviewdog 🐶}
SME ==> SAME, SEME, SOME, SMS

github-actions · 2025-01-30T15:26:56Z

hal/aarch64/exceptions.c

+		case 0b011100:
+			return "(FEAT_FPAC) Exception from a PAC Fail";
+		case 0b011101:
+			return "(FEAT_SME) Access to SME functionality trapped";


[codespell] _{reported by reviewdog 🐶}
SME ==> SAME, SEME, SOME, SMS

github-actions · 2025-01-30T15:26:56Z

hal/aarch64/pmap.c

+		}
+	}
+
+	/* Set code to read-only, everthing else XN and remove mappings past the end */


[codespell] _{reported by reviewdog 🐶}
everthing ==> everything

github-actions · 2025-01-30T15:26:56Z

hal/aarch64/arch/pmap.h

+
+#include "hal/types.h"
+
+/* Predefined virtual adresses */


[codespell] _{reported by reviewdog 🐶}
adresses ==> addresses

github-actions · 2025-01-30T15:26:56Z

hal/aarch64/arch/pmap.h

+#define VADDR_DTB     0xfffffffffff00000 /* Last 1 MB of virtual space */
+
+
+/* Architecure dependent page attributes */


[codespell] _{reported by reviewdog 🐶}
Architecure ==> Architecture

github-actions · 2025-01-30T15:41:00Z

Unit Test Results

7 958 tests ±0 7 416 ✅ ±0 40m 13s ⏱️ -15s
470 suites ±0 542 💤 ±0
1 files ±0 0 ❌ ±0

Results for commit dd3cc03. ± Comparison against base commit 4396455.

♻️ This comment has been updated with latest results.

github-actions · 2025-02-07T16:33:45Z

hal/aarch64/aarch64.h

+/* Invalidate all instruction caches to PoU */
+static inline void hal_cpuInvalInstrCacheAll(void)
+{
+	__asm__ volatile ("dsb ish\n ic iallu\n dsb ish\n isb\n");


[clang-format-pr] _{reported by reviewdog 🐶}
suggested fix

Suggested change

__asm__ volatile ("dsb ish\n ic iallu\n dsb ish\n isb\n");

__asm__ volatile("dsb ish\n ic iallu\n dsb ish\n isb\n");

Previously loop counters were counting the number of pages, while the count limit was in bytes, potentially causing a buffer overrun. JIRA: RTOS-949

Add support for ZynqMP platform. JIRA: RTOS-949

Set stack size of usrv message thread to SIZE_KSTACK. The default stack size of 2048 was insufficient on AArch64. JIRA: RTOS-949

github-actions · 2025-02-12T11:29:58Z

hal/aarch64/arch/cpu.h

+
+static inline void hal_cpuDisableInterrupts(void)
+{
+	__asm__ volatile ("msr daifSet, #3\n dsb ish \n isb");


[clang-format-pr] _{reported by reviewdog 🐶}
suggested fix

Suggested change

__asm__ volatile ("msr daifSet, #3\n dsb ish \n isb");

__asm__ volatile("msr daifSet, #3\n dsb ish \n isb");

github-actions · 2025-02-12T11:29:58Z

hal/aarch64/arch/cpu.h

+
+static inline void hal_cpuEnableInterrupts(void)
+{
+	__asm__ volatile ("msr daifClr, #3\n dsb ish \n isb");


[clang-format-pr] _{reported by reviewdog 🐶}
suggested fix

Suggested change

__asm__ volatile ("msr daifClr, #3\n dsb ish \n isb");

__asm__ volatile("msr daifClr, #3\n dsb ish \n isb");

fork: return value in child

9f9bd46

Due to exiting on different stack than current's thread in fork in child the return value was not set by threads_setupUserReturn. JIRA: RTOS-979

github-actions bot reviewed Jan 30, 2025

View reviewed changes

jmaksymowicz force-pushed the jmaksymowicz/aarch64 branch from 80df916 to 357c395 Compare February 7, 2025 16:32

github-actions bot reviewed Feb 7, 2025

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jmaksymowicz added 3 commits February 11, 2025 13:28

vm/page: fix buffer overrun in initialization

fc166eb

Previously loop counters were counting the number of pages, while the count limit was in bytes, potentially causing a buffer overrun. JIRA: RTOS-949

hal: add support for AArch64 architecture

71389e8

Add support for ZynqMP platform. JIRA: RTOS-949

usrv: increase stack size

dd3cc03

Set stack size of usrv message thread to SIZE_KSTACK. The default stack size of 2048 was insufficient on AArch64. JIRA: RTOS-949

jmaksymowicz force-pushed the jmaksymowicz/aarch64 branch from 357c395 to dd3cc03 Compare February 12, 2025 11:29

github-actions bot reviewed Feb 12, 2025

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hal: AArch64/ZynqMP port #635

hal: AArch64/ZynqMP port #635

jmaksymowicz commented Jan 30, 2025 •

edited

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github-actions bot commented Jan 30, 2025 •

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	__asm__ volatile ("tlbi vaae1is, %0" : : "r"(arg));
	__asm__ volatile("tlbi vaae1is, %0" : : "r"(arg));

	__asm__ volatile ("tlbi vae1is, %0" : : "r"(arg));
	__asm__ volatile("tlbi vae1is, %0" : : "r"(arg));

	__asm__ volatile ("tlbi vmalle1is");
	__asm__ volatile("tlbi vmalle1is");

	u64 pfr0; /* ID_AA64PFR0_EL1 */
	u64 pfr0; /* ID_AA64PFR0_EL1 */

		#define VADDR_DTB 0xfffffffffff00000 /* Last 1 MB of virtual space */


		/* Architecure dependent page attributes */

	__asm__ volatile ("dsb ish\n ic iallu\n dsb ish\n isb\n");
	__asm__ volatile("dsb ish\n ic iallu\n dsb ish\n isb\n");

	__asm__ volatile ("msr daifSet, #3\n dsb ish \n isb");
	__asm__ volatile("msr daifSet, #3\n dsb ish \n isb");

	__asm__ volatile ("msr daifClr, #3\n dsb ish \n isb");
	__asm__ volatile("msr daifClr, #3\n dsb ish \n isb");

hal: AArch64/ZynqMP port #635

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jmaksymowicz commented Jan 30, 2025 • edited Loading

Description

Motivation and Context

Types of changes

How Has This Been Tested?

Checklist:

Special treatment

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github-actions bot commented Jan 30, 2025 • edited Loading

Unit Test Results

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jmaksymowicz commented Jan 30, 2025 •

edited

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