hal/imxrt106x: fix enet PLL init

- correct clk0 enable bit
- add bypass during clock frequency change

JIRA: RTOS-507

hal/armv7m/imxrt/10xx/imxrt10xx.c

@@ -969,7 +969,7 @@ void _imxrt_ccmInitEnetPll(u8 enclk0, u8 enclk1, u8 enclk2, u8 div0, u8 div1)
 	u32 enet_pll = ((div1 & 0x3) << 2) | (div0 & 0x3);
 
 	if (enclk0 != 0) {
-		enet_pll |= 1 << 12;
+		enet_pll |= 1 << 13;
 	}
 
 	if (enclk1 != 0) {
@@ -980,10 +980,14 @@ void _imxrt_ccmInitEnetPll(u8 enclk0, u8 enclk1, u8 enclk2, u8 div0, u8 div1)
 		enet_pll |= 1 << 21;
 	}
 
-	*(imxrt_common.ccm_analog + ccm_analog_pll_enet) = enet_pll;
+	*(imxrt_common.ccm_analog + ccm_analog_pll_enet) = 1 << 16; /* enable bypass during clock frequency change */
+
+	*(imxrt_common.ccm_analog + ccm_analog_pll_enet) |= enet_pll;
 
 	while ((*(imxrt_common.ccm_analog + ccm_analog_pll_enet) & (1 << 31)) == 0) {
 	}
+
+	*(imxrt_common.ccm_analog + ccm_analog_pll_enet) &= ~(1 << 16);
 }