hal/ia32: add memoryspace, usbownership pctl commands

JIRA: RTOS-937
phoenix-rtos · Nov 22, 2024 · 275a399 · 275a399
1 parent 1eb7c70
commit 275a399
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Showing 4 changed files with 94 additions and 7 deletions.
diff --git a/hal/ia32/cpu.c b/hal/ia32/cpu.c
@@ -560,6 +560,18 @@ int hal_platformctl(void *ptr)
 			}
 			break;
 
+		case pctl_memoryspace:
+			if (data->action == pctl_set) {
+				return hal_pciSetMemorySpace(&data->memoryspace.dev, data->memoryspace.enable);
+			}
+			break;
+
+		case pctl_usbownership:
+			if (data->action == pctl_set) {
+				return hal_pciSetUsbOwnership(&data->usbownership.dev, data->usbownership.eecp, data->usbownership.osOwned);
+			}
+			break;
+
 		case pctl_reboot:
 			if (data->action == pctl_set) {
 				if (data->reboot.magic == PCTL_REBOOT_MAGIC) {

diff --git a/hal/ia32/pci.c b/hal/ia32/pci.c
@@ -84,19 +84,24 @@ static int _hal_pciGetCaps(pci_dev_t *dev, void *caps)
 }
 
 
-int hal_pciSetBusmaster(pci_dev_t *dev, u8 enable)
+/* Sets a bit in PCI configuration command register */
+int _hal_pciSetCmdRegBit(pci_dev_t *dev, u8 bit, u8 enable)
 {
 	spinlock_ctx_t sc;
 	u32 dv;
 
-	if (dev == NULL)
+	if (dev == NULL) {
 		return -EINVAL;
+	}
 
 	hal_spinlockSet(&pci_common.spinlock, &sc);
 	dv = _hal_pciGet(dev->bus, dev->dev, dev->func, 1);
-	dv &= ~(1 << 2);
-	if (enable)
-		dv |= (1 << 2);
+	if (enable != 0) {
+		dv |= (1 << bit);
+	}
+	else {
+		dv &= ~(1 << bit);
+	}
 	_hal_pciSet(dev->bus, dev->dev, dev->func, 1, dv);
 	hal_spinlockClear(&pci_common.spinlock, &sc);
 
@@ -106,6 +111,59 @@ int hal_pciSetBusmaster(pci_dev_t *dev, u8 enable)
 }
 
 
+int hal_pciSetBusmaster(pci_dev_t *dev, u8 enable)
+{
+	return _hal_pciSetCmdRegBit(dev, 2, enable);
+}
+
+
+int hal_pciSetMemorySpace(pci_dev_t *dev, u8 enable)
+{
+	return _hal_pciSetCmdRegBit(dev, 1, enable);
+}
+
+
+int hal_pciSetUsbOwnership(pci_dev_t *dev, u8 eecp, u8 osOwned)
+{
+	spinlock_ctx_t sc;
+	u32 dv;
+	u8 reg = eecp >> 2U; /* eecp is a pci config offset */
+
+	if (dev == NULL) {
+		return -EINVAL;
+	}
+
+	hal_spinlockSet(&pci_common.spinlock, &sc);
+	dv = _hal_pciGet(dev->bus, dev->dev, dev->func, reg);
+	if (osOwned != 0) {
+		dv |= (1 << 24);
+
+		/* ensure interrupt disable bit is set to false */
+		_hal_pciSetCmdRegBit(dev, 10, 0);
+	}
+	else {
+		dv &= ~(1 << 24);
+	}
+	_hal_pciSet(dev->bus, dev->dev, dev->func, reg, dv);
+
+	for (;;) {
+		dv = _hal_pciGet(dev->bus, dev->dev, dev->func, reg);
+		if ((osOwned != 0) && ((dv & (1 << 24)) != 0) && ((dv & (1 << 16)) == 0)) {
+			break;
+		}
+
+		if ((osOwned == 0) && ((dv & (1 << 24)) == 0) && ((dv & (1 << 16)) != 0)) {
+			break;
+		}
+	}
+	hal_spinlockClear(&pci_common.spinlock, &sc);
+
+	dev->command = dv & 0xffff;
+
+	return EOK;
+}
+
+
 int hal_pciGetDevice(pci_id_t *id, pci_dev_t *dev, void *caps)
 {
 	spinlock_ctx_t sc;

diff --git a/hal/ia32/pci.h b/hal/ia32/pci.h
@@ -22,6 +22,12 @@
 extern int hal_pciSetBusmaster(pci_dev_t *dev, u8 enable);
 
 
+extern int hal_pciSetMemorySpace(pci_dev_t *dev, u8 enable);
+
+
+extern int hal_pciSetUsbOwnership(pci_dev_t *dev, u8 eecp, u8 enable);
+
+
 extern int hal_pciGetDevice(pci_id_t *id, pci_dev_t *dev, void *caps);
 
 

diff --git a/include/arch/ia32/ia32.h b/include/arch/ia32/ia32.h
@@ -76,7 +76,7 @@ typedef struct {
 
 typedef struct {
 	enum { pctl_set = 0, pctl_get } action;
-	enum { pctl_pci = 0, pctl_busmaster, pctl_reboot, pctl_graphmode } type;
+	enum { pctl_pci = 0, pctl_busmaster, pctl_memoryspace, pctl_reboot, pctl_graphmode, pctl_usbownership } type;
 
 	union {
 		struct {
@@ -87,9 +87,20 @@ typedef struct {
 
 		struct {
 			pci_dev_t dev;
-			int enable;
+			short enable;
 		} busmaster;
 
+		struct {
+			pci_dev_t dev;
+			short enable;
+		} memoryspace;
+
+		struct {
+			pci_dev_t dev;
+			short osOwned;
+      short eecp;
+		} usbownership;
+
 		struct {
 			unsigned int magic;
 			unsigned int reason;