CPU Exceptions #1004
Replies: 48 comments 26 replies
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Got a compiler error while trying out the code from listing.
The error is obvious to fix. P.S. My code has the A dedicated github issue : #452 |
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Yeah, we released a new x86_64 version with this renaming a few days ago. I thought it's better to wait a bit before updating the post to avoid breakage for the users on older versions. Normally the deprecation only causes a warning instead of an error, so I thought this wouldn't break new users. The question is why it's an error for you. Are you explicitly using deny(warnings) or something like that? |
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Yes, that's the case. I've continued the discussion (a few more questions from me) in a dedicated ticket. |
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I consider it strange to write these exception codes to main.rs or bin/*.rs. Why not write them to lib.rs which can pub a code. |
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Because we want to do different things on an exception (compare the implementations of the Edit: We moved the exception handlers to an |
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Thank you first for this awesome blog post! Good luck, and thanks again! |
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@k0pernicus You're right, thank you! Fixed in 442da8c. |
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Why does |
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Good catch! Removed in d9f3b3d. |
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Hello, and thanks for your work on this blog series! I've been learning a lot by working through it. One thing I was unsure about in this section, is why does the integration test not rely on our new |
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@JoshMcguigan Good point! I think I already had the test for double faults in mind when writing this post. The double fault test makes sense because it checks that we have a correct GDT and TSS setup, but the test in this post requires no previous setup so it really tests only the x86_64 crate. I don't think that we can reuse the |
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Is there a way to define your own interrupts with dedicated handlers (without colliding with the hardware interrupts to implement later) ? |
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@AntoineSebert You mean software interrupts? Yes, you can just use any of the higher IDT entries (i.e. the entries not used for exceptions or hardware interrupt). |
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@phil-opp |
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@AntoineSebert No, the
Yes. For example, you could set |
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@midwinter1993 LLVM did the magic expected of it. It only saved registers that are clobbered by your function (hence rax). All other register are left unchanged hence there’s no need of saving and restoring them. |
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@GuillaumeDIDIER |
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@midwinter1993 I just pushed a3eeb1d to make this more clear in the post. Thanks for asking! |
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Hi Phil, I've checked your branch for this post and verified there's no difference in code, cargo.toml nor the json file. I've also commented the int3() line out and sprinkled some printlns here and there to see if the "right" functions are exectuted in my interrupts.rs and lib.rs files, so the functions to load the IDT are being hit. Any ideas? |
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The reboot looks like a triple fault (which is not surprising given that we don't have any double fault handler around). |
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Hi @RoidoChan, great to hear that you like the blog!
Have you tried cloning the repo and running it directly? Sometimes it's a small typo or a file that one didn't think of that is causing the issue. Also, if you have your code online somewhere I can take a look and try to reproduce it.
Sounds like something is wrong with your IDT setup. You can try passing Hope this helps! Please let me know what the issue was when you find it. |
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Hi @GuillaumeDIDIER Hi @phil-opp, I moved some "use" statements around in the .rs files and it started to work for some reason? Worst thing is I didn't do a commit of the buggy version, so I can't diff and see exactly was causing the issue. Sorry! Thanks so much for your time, and again the blog is great. Learning some comp sci fundamentals I never really understood, despite working professionally in games for some years. signed up as a Patron! Keep it going! |
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@RoidoChan
Yeah, I found
No worries, great to hear that it's working now!
It makes me happy to hear that. Thanks a lot for supporting me! |
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Hi @phil-opp, first things first, a lot of thanks for your posts! I'm getting an issue with the x86-interrupt:
But I do have the |
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Is this only for computers with x86_64 cpu type. If yes how can we make it for both amd and intel |
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still a great blog/tutorial even after 4 years! |
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Question for the core team: If you already have a handler for a fault that's leading to a double fault, then why would the double fault handler still get invoked instead of one of the precursor fault handlers?
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I am surprised that the interrupt test shows a virtual address in the console. So far no paging has been enabled so how can we have a virtual address? Is it because the function which does the printing assumes the paging is enabled and thus has a default printing? |
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Hi Phil, |
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Hey, Here are two issues I encountered while doing the "Catching Exceptions" post of the first edition, coming from the second edition only for the exception part:
In the x86_64 crate its
The x86_64 crate's version I used for reference is Have a great day! :) |
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This is a general purpose comment thread for the “CPU Exceptions” post.
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