Skip to content
View perehinik's full-sized avatar

Block or report perehinik

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. textolite textolite Public

    Text editor.

    TypeScript 3

  2. Logic_Analyzer_PCB Logic_Analyzer_PCB Public

    KiCad PCB project of Logic Analyzer

    ANTLR 36 7

  3. FTDI_FT2XX_FIFO_Terminal_Python FTDI_FT2XX_FIFO_Terminal_Python Public

    Terminal for communication with FT IC in FIFO mode, tested with FT232H

    Python 7 2

  4. Relay_Tester_User_Interface Relay_Tester_User_Interface Public

    User interface for relay tester, C#

    C# 2

  5. SDRAM_Controller SDRAM_Controller Public

    Verilog SDR SDRAM controller for FPGA Xilinx and Lattice

    VHDL 16 3

  6. Logic_Analyzer_User_Interface Logic_Analyzer_User_Interface Public

    User interface for logic analyzer. Made on Python

    Python 3 3