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romstage.c: force CLK3 to be always on #11

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merged 1 commit into from
Sep 12, 2016

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@pietrushnic pietrushnic merged commit 9cac328 into pcengines:apu2b-20160304 Sep 12, 2016
miczyg1 pushed a commit that referenced this pull request May 28, 2019
This patch adds a workaround for Samsung C-die 2G/4G memory chips.
For unknown reasons, some boards with Samsung LP3 memory chips
could not pass early CS/CMD training. MRC has to change the
granularity from 16 ticks to 8 ticks, which implies bad margin
with this memory chip. Another way is to enhance the drive
strength for CS. This patch is to enhance the drive strength for CS
and CMD. Enhancing the drive strength for CMD could gain margin abaout
3 more ticks. Root cause needs to be further investigated with memory
vendor.

BUG=b:131177542
BRANCH=None
TEST=USE=fw_debug emerge-atlas chromeos-mrc coreboot chromeos-bootimage
     & check the MRC log to ensure correct Rcomp values are passed to
     MRC. Tested with board ID #8 and #11.

Change-Id: I9ea3ceda8dc8bf781063d3c16c7c2d9b44e5ddd6
Signed-off-by: Gaggery Tsai <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32695
Tested-by: build bot (Jenkins) <[email protected]>
Reviewed-by: Caveh Jalali <[email protected]>
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