Add example code screenshot to README

README.md

@@ -3,6 +3,8 @@ A Hardware Description Language focussed on strong type and temporal safety feat
 
 Main Inspirations: [TL-Verilog](https://arxiv.org/abs/1811.01780), [Filament](https://rachitnigam.com/files/pubs/filament.pdf), [Spade](https://spade-lang.org/), [Rust](https://www.rust-lang.org/)
 
+![SUS LSP Example](philosophy/images/susLSPExample.png)
+
 ## Core philosophy
 This project is an attempt to create a safety-first, correct-by-default HDL. It must make programming easier and safer without sacrificing on low level control. Much akin to what Rust is for the software industry. 
 

test.sus

@@ -730,15 +730,17 @@ module contains_submodule_submodule : int a, int b, int c -> int r {
 module cross_int {
 	interface in : int i'0
 	interface out : -> int o'0
+	o = 1
 }
 
 module cross_memory {
 	interface in : bool[20][512] i'0
 	interface out : -> bool[20][512] o'0
+	o[0][0] = true
 }
 
 module offset_backwards : bool i'0 -> bool o'-5 {
-
+	o = true
 }
 
 module DUAL_PORT_MEM {